Making the right Zigbee wireless system partitioning decisions

Thomas Barber, Silicon Labs

May 19, 2013

Thomas Barber, Silicon LabsMay 19, 2013

When developing a 2.4 GHz ZigBee wireless networking application, designers are often faced with a system partitioning choice: What is the optimal level of integration for a ZigBee connectivity and network processing solution? From a performance, power and cost perspective, what makes the most sense – a ZigBee system-on-chip (SoC) device that combines a 2.4 GHz wireless transceiver and a processing core into a single-chip solution, or discrete approaches involving separate transceivers and host processors?

Before addressing these questions, let’s take a closer look at ZigBee technology. Based on the IEEE 802.15.4 MAC/PHY specification for low-power wireless networks, ZigBee extends IEEE 802.15.4 by adding a mesh networking communications protocol and applications profiles that allow devices to fully interoperate. ZigBee uses a highly reliable, scalable mesh networking protocol that can support thousands of nodes. ZigBee applications profiles define a common language for home/commercial automation, smart energy, health care and retail devices. ZigBee also provides testing and certification of devices to ensure interoperability from the radio through the application layer.

ZigBee has been designed as a highly reliable, low-cost, low-power wireless networking solution for sensor and control networks. The choice of system partitioning ultimately has a significant impact on the network performance, power consumption and cost of a ZigBee solution.

System partitioning
Figure 1 shows the three basic system partitioning options: the ZigBee SoC approach, a ZigBee network coprocessor (NCP) plus host processor, and ZigBee transceiver plus host processor.


Figure 1: ZigBee system partitioning options

In an SoC design, the IEEE 802.15.4 compliant radio is a peripheral to the embedded processor, and all of the packet processing and applications processing is performed within the single chip. The SoC typically includes hardware peripherals for the microprocessor to support computationally intensive functions such as AES encryption.

In an NCP design, the ZigBee stack operates on the radio and network processor chip, which is then connected to a host processor typically using a SPI or UART interface. The host is only active for those packets either sent or to be received by the application on that device. For packets that are routed, all packet processing including security processing is done on the network processor without interrupting the host processor. The impact of SPI or UART processing time would therefore only be expected at the source or destination of a packet.

A ZigBee transceiver includes only the RF transceiver and the timing-critical MAC/PHY functions, while a host processor supports the upper layers of the MAC, network protocol and applications code. All packets must be moved to the host for processing. Those packets that are only to be routed are moved to the host and then back to the radio to retransmission, typically though a UART or SPI port. Often the AES encryption operations are included on the transceiver chip; therefore, additional UART or SPI transfers are required to support the security processing.

Network Performance
Throughput and latency are important considerations to ensure the network will meet the design goals for the product. Throughput is a measure of how much data traffic the network can support and is a key metric because it determines the scalability of the network. Latency is a measure of how quickly messages are passed between nodes and is a key metric because it determines the responsiveness of the network. Throughput and latency are both a function of the device partitioning and must be considered in the system architecture.

ZigBee is a hybrid mesh networking protocol that includes a backbone of routers that are always active and end devices that are normally asleep. The routers are responsible for passing messages between the end devices or from end devices to a central controller. The throughput and latency of a ZigBee network is a function of how quickly routers can process data packets and forward them to the proper destination.

The efficiency of the routers is a function of the system partitioning. If the system uses an SoC or NCP, all of the routing is handled without needing to wake or interrupt the host processor. Packets are typically forwarded within 5-10 ms. If the system uses a transceiver, the transceiver needs to wake or interrupt the host processor to process each packet. The wake or interrupt latency can be >100 µs.

In addition, the packet data must be transferred between the transceiver and host processor. ZigBee packets can be up to 127 bytes (1016 bits) so transferring a packet to the host processor and back to the transceiver can take 0.5-4 ms at typical SPI/UART data rates. ZigBee uses AES encryption both at the MAC and network layers and sometimes even at the application layer. Additional UART or SPI data transfers will be required if either the host or the transceiver do not support efficient AES encryption.

Figure 2 shows the impact of system partitioning on network performance for a small 5-byte payload where AES encryption is only supported in the ZigBee transceiver. The latency of a single hop is 10 ms in a network that uses an SoC or NCP and 20 ms in a network that uses a transceiver.


Figure 2: Latency versus system partitioning

Since it takes each node twice as long to process a packet, the throughput of the network using transceivers has been reduced by 50 percent, which reduces the maximum number of devices that can be supported at a given activity level by 50 percent. For timing-sensitive applications such as lighting, the increased latency will limit the maximum number of hops allowed, reducing the scalability and reliability of the network.



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