Use Cirrus Logic's CS556x/7x/8x ADCs to improve DNL and noise in control system designs

Rich Wegner, Cirrus Logic

December 27, 2007

Rich Wegner, Cirrus Logic

This "Product How-To" article focuses how to use a certain product in an embedded system and is written by a company representative.

ADCs have long been a key element in the design and implementation of critical systems for scientific, industrial, medical and consumer applications. With both product feature sets and performance demands escalating relentlessly, designers are always looking for more cost-effective methods to achieve the desired measurement results from their data converter circuits.

A widening range of complex designs such as ATE, medical instrumentation and monitoring devices, data acquisition systems, laboratory instruments and programmable logic controllers (PLCs) for industrial automation, all depend on high-resolution ADCs to meet application objectives.

It is the ADC that provides the link between the "real world" of analog phenomena and the "processing world" that uses digital information. The fundamental requirements for ADCs always revolve around resolution, accuracy and bandwidth. Other important considerations that must be considered in selecting an ADC are signal-to-noise performance, distortion and latency.

Many applications need rapid responsiveness from ADCs to process high frequency or continuous readings from various sensors. The ability to efficiently multiplex multiple signals within the ADC is becoming increasingly important.

This is due to the growing requirement to handle multiple analog inputs within the same device, such as designing PLCs that are able to simultaneously monitor and integrate real-time inputs from multiple sensors within a production environment.

Many conventional ADC architectures have inputs that present difficult drive requirements, demanding costly high-performance input buffers to deliver the needed responsiveness for continuous-processing scenarios.

Some ADC architectures even impose "mandatory quiet time" in which the system can't access the ADC's output during the sampling process, further complicating the design task.

Of course, other key considerations in any component selection include the cost of the device itself and any support circuitry required to assure its proper functioning within the overall design.

This can be a particularly important issue with ADCs, especially when used in a high-performance muxed environment because the required support circuitry can vary significantly depending on the type of ADC selected.

For example, if the ADC architecture doesn't inherently provide good noise rejection and measurement accuracy, it can require overdesigning the circuit to meet performance goals.

Designs based on conventional successive approximation register (SAR) devices can present particular challenges because the board space, costs and power requirements associated with designing input buffers can quickly outweigh the apparent low-power specifications for the SAR itself.

All of these factors play a critical role in the cost-effective achievement of design goals.

Traditional SAR approach
The types of high-performance applications mentioned have been designed around ADCs using a SAR architecture, which provides a series of "snapshots" of the data at successive points in time. SARs have generally been targeted at applications that require fast response and low latency.

However, because SARs are sensitive to noise and have relatively low dynamic nonlinearity (DNL) performance, the need for significant support circuitry often drives up the overall cost and complexity of SAR-based designs.

Poor linearity performance presents particularly challenging problems because this error cannot be averaged out by oversampling of the signal. In too many cases, design engineers must compensate by overspecifying the SAR and overdesigning the system to make up for SARs' poor DNL performance.

Similarly, the higher noise sensitivity of SARs and limited noise-rejection capabilities present additional design challenges, especially in the inherently noisy environments for many deployments, such as PLCs on production floors or clusters of medical instrumentation in close proximity.

In contrast, ADCs using DeltaSigma architectures have traditionally been able to deliver improved DNL and noise performance, and allow for much less complex support circuitry. DeltaSigma ADCs have not previously been considered appropriate for use in high-performance applications requiring low latency and high conversion rates to achieve wide signal bandwidth. However, such "conventional wisdom" no longer holds true.