Basics of real-time measurement, control, and communication using IEEE 1588: Part 5
Appling 1588 to Central Office
Timing Distribution
In the current telecommunications system, the central office is the
location where local access terminates and connects to trunk links to
other central offices, or to long-distance networks.
Within the central office, it is customary to distribute frequency via the Building Integrated Timing Supply, or BITS. Most BITS derive frequency from a GPS installation with backup from land-line-based sources. The BITS system currently supports only frequency distribution. Epoch or time is normally distributed using other techniques such as NTP.
If more accurate epoch information becomes necessary within the central office, the use of IEEE 1588 to distribute both time and frequency over the building LAN becomes more attractive.
Possible uses are for precise logging and billing of data in packet-based services. As in both industrial automation and test and measurement, a precise time service will be used for timestamping and logging anomalous events.
It is quite likely that future packet-based services to homes and enterprises will require time as well as frequency. VoIP services will be enhanced by precise timing. There is also considerable discussion in the home entertainment community about providing synchronization services within the home (see, for example, the tutorial of Teener et al. [92]).
Simplifying TDM Circuit Emulation
Circuit emulation is a technique for carrying existing time division
multiplexed (TDM) telecommunications traffic over packet-based
networks. Carriers are replacing traditional T1 and E1 TDM links with
packet-based links, but must continue to support customers using
TDM-based services, such as existing T1 lines, PBX, and fax.
Circuit emulation works by creating a tunnel for TDM data through the packet network. Equipment is provided at each end of a packet-based link to packetize or de-packetize the TDM data. The difficulty is that the TDM links depend on synchronous clocks at both the transmitting and receiving ends of the link.
This timing is lost in the packet-based link and, if uncorrected, will result in corrupted or degraded performance. For example, if the clock of a receiving T1 link is running slower than the clock in the transmitting link, then packets will be dropped.
TDM networks have very tight requirements on the allowed variation between the transmitting and receiving clocks. These requirements are defined in a number of ITU recommendations, including G.823 and G.824.
Frequency differences between these clocks are characterized by high-frequency jitter, which is fairly easy to filter, and low-frequency wander, which is much more difficult to eliminate. Frequency wander between two clocks will lead to dropped packets (slips) unless sufficiently large data buffers are provided.
Buffers add cost, introduce latency, and can accommodate only a finite level of wander, leading the ITU to specify the maximum number of slips such that no more than 125 microseconds of data is lost in any 70-day period.
There are currently two techniques used to provide the needed frequency synchronization. The first is called adaptive clocking. In adaptive clocking, the receiver adjusts its clock to match the rate of incoming information by averaging the arrival rate or the inter-arrival times of incoming packets, or by monitoring the fill levels of the buffers.
This technique is subject to the same difficulties facing IEEE 1588, namely, packet loss, latency fluctuations, and changing distribution of fluctuations.
However, the circuit emulation services are unlikely to be able to use the very long-term averaging algorithms available to an IEEE 1588 installation, either due to the lifetime of the circuit, or the need to more closely track the actual information rates.
The second technique is called differential clock recovery. In this case, a high-quality clock, such as a primary reference source (PRS), is provided at both ends of the packet network.
The difference between the TDM service frequency and the PRS at the sending end is encoded in the TDM packets transmitted over the packet-based network. At the receiving end, this differential information is used to reconstruct the TDM timing based on the local PRS.
This will work in central offices, but not in the planned extensions using Ethernet links between the central office and the emulated services in customer premises. IEEE 1588 can provide the required timing in these situations.
Uses in telecom equipment internal
timing
The last example to be discussed is to use IEEE 1588 to distribute time
within telecommunications equipment. Current designs of this equipment
are a mixture of centralized functions and line cards specific to each
link terminating at the equipment.
Internal synchronization often involves precision oscillators on
line cards as well as in the centralized functions. IEEE 1588 has been
proposed as a means of distributing time from a few very stable central
oscillators to less expensive but more numerous oscillators on the line
cards. The IEEE 1588 traffic could be carried either on the control
plane or in-line with the data.
To read Part 1, go to "The varieties of system temporal specifications."
To read Part 2, go to "Overview of the 1588 clock synchronization standard."
To read Part 3, go to "Master-slave Synchronization Hierarchy"
To read Part 4, go to "Achieving submicrosecond synchronization accuracy"
Used with permission of its publisher, Springer Science and
Business Media, this series of articles is based on material from "Measurement,
Control and Communication Using IEEE 1588," by John C. Eidson and
can be purchased on line.
John C. Eidson, Ph.D., received a B.S. and an M.S. from Michigan State University and a Ph.D. from Stanford University, all in electrical engineering. He held a postdoctoral position at Stanford for two years, spent six years with the Central Research Laboratory of Varian Associates, and joined the Central Research Laboratories of Hewlett-Packard in 1972. When HP split in 1999, he transferred to the Central Research Laboratory of Agilent Technologies. Dr. Eidson was heavily involved in IEEE 1451.2 and IEEE 1451.1 and is the chairperson of the IEEE 1588 standards committee and a life fellow of the IEEE.
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