A mixed signal approach to debugging DDR DRAM interfaces

Min-Jie Chong

December 14, 2009

Min-Jie Chong

The importance of R/W isolation
Ability to isolate the read and write operations is critical for memory controller and DDR chip validation task. Since the read and write operations on the DDR bus use the same strobe and data signals for communication, inability to separate the operations means the signals captured on the oscilloscope would consist of both operations.

This would not allow effective characterization of the memory controller and the DDR chip. Again, the separation would need to rely on the control signals for separating the read and write commands.

But with the limited oscilloscope channels, this task can be daunting. Besides that, are there also other more efficient methods that can be used really effective to separate the read and write operations?

If the earlier challenges are not enough, do not forget that you still need to spend time validating each of the test parameters defined in the JEDEC specification.

Because the list of tests can be long, it is often difficult to exhaustively characterize every test. Making the measurements by hand can be bad enough, but could be worse if the results must be manually recorded and formatted in a test report. Are there tools that are already developed that can perform the measurements?

On top of that, troubleshooting the failures related to physical and protocol layers can be tricky. Typically, a logic analyzer and oscilloscope can be used together for this purpose, but this would increase the cost and learning curve.

With all the described challenges with a conventional scope, it is no wonder there is a huge need for new oscilloscope that goes beyond just 4 input channels, as well as new capabilities for validating and debugging DDR interface.

New capabilities with MSO
The MSO, a non-conventional oscilloscope architecture, provides not only the four analog input channels but integrated logic channels where both channels are time correlated internally in the instrument (Figure 2, below).

Figure 2: With an MSO, displayed are the tests that are passing (marked clear), failing (marked red) and marginally passing (marked yellow). Getting the results quickly helps you determine which part of the design has to be fixed.

This can be imagined as a hybrid tool comprising of a conventional oscilloscope and a logic analyzer. With the additional channels, you can now connect the control signals to the MSO's logic channels and effortlessly trigger on different commands such as activate, precharge, read and write, while freeing the analog channels for making physical layer measurements on the signals that matter.

Now, other types of protocol measurements that involve complex triggering on multiple control signals is possible with MSO, such as include Write Latency and Auto-Precharge parameters. The MSO also provides state machine and operation decode information for command on the DDR interface. Before, you might have to hand decode the commands but the MSO can provide automated decoding of these commands.

This quickly tells you the type commands that are present on the trace, allowing you to focus on the validation and debug. With this, you can also quickly tell the oscilloscope to isolate a specific command on the bus. For instance, you can trigger on Write commands with the logic channels and make parametric measurements on the strobe and data signals. This allows you to validate conditions that were only possible with a logic analyzer.

The logic channels also allow you to look at other additional signals at the same time such as the address and data signals, which are not possible using the conventional oscilloscope.

With this ability, you can be more effective to look at the other information on the DDR interface. This can be a powerful debugging tool when used together with the analog channel because the advanced cross triggering capability of the analog and logic channels allow you to find physical and protocol layer issues quickly.

By identifying the type of failures occurring on your DDR interface, the issues can be quickly resolved at the design level.