PRODUCT HOW-TO: Using standards-based tools to scale chip designs to next-gen geometries

Rich Morse and Mitch Heins

June 8, 2010

Rich Morse and Mitch Heins

Dealing with layout challenges
Although the custom layout and hand-routing approach was able to meet performance requirements, it was becoming increasingly more difficult to complete the next generation of custom digital blocks in a reasonable period of time.

As the designs got larger and more complex, layout designers encountered serious routing problems and found themselves designing-in white space (open areas) for routing channels, giving up density to make manual and point-to-point automated routing manageable in increasingly large blocks.

While the design team could still achieve performance targets, it often came at the expense of increased area, which was less than ideal given the cost-sensitivity of their market segment. In addition, the amount of time required to complete the design precluded trying more than a single layout.

A further challenge was introduced with the design team’s move to 40nm manufacturing processes to accommodate the increased performance requirements. At this node, blocks became too big (too many nets) and design rules too advanced for hand-routing and existing automated custom routing solutions.

There were no large scale custom routers that could provide the deep sub-micron DRC-clean and DFM-aware routing required for advanced processes.

The team initially attempted to use a hybrid flow, hand routing critical nets using the layout editor as before, and then using the digital router in their APR flow that supports advanced DRC rules to complete the non-critical nets.

Unfortunately, moving in and out of multiple tool sets was counter- productive. No matter how efficient the individual operations were, the custom and digital design domains did not work well together. In addition, this method was not interactive and caused the team to lose both hierarchy and connectivity information. More often than not, the automated router also re-routed some of the painstakingly-drawn critical nets, requiring extensive hand edits or yet another cycle through the router, or possibly both.

As a result, the design team spent six weeks moving the design back and forth, in order to converge on an acceptable, albeit sub-optimal, result. Automated routing, even for non-critical nets, might have improved the team’s productivity had it not impeded their ability to work iteratively. Also, there was no way to represent partial pre-routes and the sophisticated spacing constraints needed to guide the APR tools.

This, in turn, lead to bad parasitic interactions within the custom blocks that required laborious manual re-routes and multiple lengthy re-runs.

While automation typically improves productivity, in this case, it made a difficult process longer because designers could not control the results. Indeed, hand-edits of critical nets in a fully routed layout can take longer than routing by hand initially.

The team concluded that in order to achieve optimum results in less time it would require a heterogeneous environment that maintains hierarchy, connectivity and design integrity through controllable automation. Interoperability saves the day.

Figure 2: Si2 has made available an interoperable database for EDA tools called OpenAccess (OA).

The standards organization Si2 has made available an interoperable database for EDA tools called OpenAccess (OA) that has in recent years become the standard for custom design (Figure 2, above).