PRODUCT HOW-TO: Using standards-based tools to scale chip designs to next-gen geometries

Rich Morse and Mitch Heins

June 8, 2010

Rich Morse and Mitch Heins

Layout for large digital IC designs is generally created using highly automated place-and-route (APR) tools. Although there are trade-offs for using APR instead of custom layout, the speed and confidence offered by APR far out weigh the compromises in area or performance for most designs.

But designs that require the utmost in performance and/or the smallest possible area are still done “by hand” using custom IC layout methodologies. In the next generation of custom chips, complicated rules, tight time-to-market schedules, and the sheer size and complexity of designs are making full-custom digital blocks increasingly difficult to implement.

Fully-automated APR flows cannot offer the kind of interactive control of the layout and routing that is necessary. Designers need a highly-automated yet controllable full custom digital IC design flow that optimizes performance, speed and area.

This article details how one digital IC design team at a large fabless semiconductor company in the consumer product market is leveraging standards-based tool interoperability to maintain the benefits of hand layout for large, performance-sensitive 40nm designs.

The team has deployed the integration capabilities made possible by the Silicon Integration Initiative’s (Si2) Open Access (OA) interoperability standardization effort with tools from multiple vendors to form a more productive custom IC layout flow.

Controllable automation
In designing high-volume storage solutions, the design team has for many years deployed custom IC layout automation for its analog and custom digital designs.

While analog designers have always used custom design methodologies, it is typically only when performance, power, speed or area requirements exceed the capabilities of APR tools that digital design teams turn to custom design tools and flows.

For optimal performance and cycle time, engineers use tools that employ advanced controllable automation techniques to create custom digital designs much faster and with less effort.

These include an advanced schematic driven layout (SDL) flow that uses highly configurable, process-independent parameterized cell technology and a device-level floor planning tool that offer the speed and control necessary to achieve the best possible performance and density without having to change design style or compromise the quality of the result.

Figure 1: Flight lines show connectivity and guide rule-driven manual routing.

Using the flight lines generated from the connectivity automatically carried over from the schematic (Figure 1, above ), the engineers then use the built-in rule-driven interactive router to wire critical nets by hand to meet demanding clock rate requirements that exceed 2GHz.

At this performance level, the routing of an individual net is especially sensitive to its environment and interactions with other routes, nets and even other layers.

To balance all of these elements, it is necessary for the design team to interact with all elements of their design environment. When handrouting, the design team is able to route, extract and evaluate the critical nets for timing and then modify them until the desired values are obtained.