A guide to VHDL for embedded software developers: Part 1 – Essential commands

Peter Wilson

July 19, 2011

Peter Wilson

Architecture: model behavior
While the entity describes the interface and parameter aspects of the model, the architecture defines the behavior.

Basic definition of an architecture. There are several types of VHDL architecture and VHDL allows different architectures to be defined for the same entity. This is ideal for developing behavioral, Register Transfer Level RTL and gate Level architectures that can be incor porated into designs and tested using the same test benches. The basic approach for declaring an architecture could be as follows:

architecture behaviour of test is
..architecture declarations
Begin
...architecture contents
end architecture behaviour;

OR

architecture behaviour of test is
..architecture declarations
begin
...architecture contents
end behaviour;

Architecture declaration section
After the declaration of the architecture name and before the begin statement, any local signals or variables can be declared. For example, if there were two internal signals to the architecture called sig1 and sig2, they could be declared in the declaration section of the model as follows:

architecture behaviour of test is

signal sig1, sig2 : bit;

begin

Then the signals can be used in the architecture statement section.

Architecture statement section
VHDL architectures can have a variety of structures to achieve different types of functionality. Simple combinatorial expressions use signal assignments to set new signal values as shown below:

out1 <= in1 and in2 after 10 ns;

Note that for practical design, the use of the ‘after 10 ns’ is not synthesizable. In practice, the only way to ensure correct synthesizable design is to either make the design delay insensitive or synchronous.

The design of combinatorial VHDL will result is additional delays due to the technology library gate delays, potentially resulting in glitches or hazards.

An example of a multiple gate combinatorial architecture using internal signal declarations is given below:

architecture behavioural of test is

signal int1, int2 : bit;

begin

int1 <= in1 and in2;
int2 <= in3 or in4;
out1 <= int1 xor int2;

end architecture behavioural;

Process: the basic functional unit in VHDL
The process in VHDL is the mechanism by which sequential statements can be executed in the correct sequence, and with more than one process, concurrently. Each process consists of a sensitivity list, declarations and statements. The basic process syntax is given below:

process sensitivity_list is
   ... declaration part
begin
   ... statement part
end process;

The sensitivity list allows a process to be activated when a specific signal changes value, for example a typical usage would be to have a global clock and reset signal to control the activity of the process, for example:

process (clk, rst) is
begin
   ... process statements
end process;

In this example, the process would only be activated when either clk or rst changed value. Another way of encapsulating the same behavior is to use a wait statement in the process so that the process is automatically activated once, and then waits for activity on either signal before running the process again. The same process could then be written as follows:

process
begin
    ... process statements
    wait on clk, rst;
end process;

In fact, the location of the wait statement is not impor tant, as the VHDL simulation cycle executes each process once during initialization, and so the wait statement could be at the start or the end of the process and the behavior would be the same in both cases.

In the declaration section of the process, signals and variables can be defined locally as described previously, for example a typical process may look like the following:

process (a) is
   signal na : bit;
begin
   na <= not a;
end process;

With the local signal na and the process activated by changes on the signal a that is externally declared (with respect to the process).

Basic variable types and operators
Constants. When a value needs to be static throughout a simulation, the type of element to use is a constant. This is often used to initialize parameters or to set fixed register values for comparison.

A constant can be declared for any defined type in VHDL with examples as follows:

constant a : integer := 1;
constant b : real := 0.123;
constant c : std_logic := ‘0’;

Signals. Signals are the link between processes and sequential elements within the processes. They are effectively ‘wires’ in the design and connect all the design elements together.

When simulating signals, the simulator will in tur n look at updating the signal values and also checking the sensitivity lists in processes to see whether any changes have occur red that will mean that processes become active.

Signals can be assigned immediately or with a time delay, so that an event is scheduled for sometime in the future (after the specified delay).

It is also important to recognize that signals are not the same as a set of sequential program code (such as in C), but are effectively concurrent signals that will not be able to be considered stable until the next time the process is activated.

Examples of signal declaration and assignment are shown below:

signal sig1 : integer := 0;
signal sig2 : integer := 1;
sig1 <= 14;
sig1 <= sig2;
sig1 <= sig2 after 10 ns;

Variables. While signals are the external connections between processes, variables are the internal values within a process. They are only used in a sequential manner, unlike the concur rent nature of signals within and between processes. Variables are used within processes and are declared and used as follows:

variable var1 : integer := 0;
variable var2 : integer := 1;
var1 := var2;

Notice that there is no concept of a delay in the variable assignment – if you need to schedule an event, it is necessary to use a signal.