A guide to VHDL for embedded software developers: Part 1 – Essential commands

Peter Wilson

July 19, 2011

Peter Wilson

Boolean operators. VHDL has a set of standard Boolean operators built in, which are self-explanatory. The list of operators are and, or, nand, not, nor, xor. These operators can be applied to BIT, BOOLEAN or logic types with examples as follows:

out1 <= in1 and in2;
out2 <= in3 or in4;
out5 <= not in5;

Arithmetic operators. There are a set of arithmetic operators built into VHDL which again are self-explanatory and these are described and examples provided in Table 1, below.

Table 1: Basic arithmetic operators

Comparison operators. VHDL has a set of standard comparison operators built in, which are self-explanatory. The list of operators are =,/=,<,<=,>,and >=. These operators can be applied to a variety of types as follows:

in1 < 1
in1 /= in2
in2 >= 0.4

Shifting functions. VHDL has a set of six built in logical shift functions which are summarized in Table 2 below:

Table 2: Basic logical shift functions

Concatenation. The concatenation function XE ‘VHDL:concatenation’ in VHDL is denoted by the & symbol and is used as follows:

A <= ‘1111’;
B <= ‘000’;
out1 <= A & B & ‘1’; -- out1 = ‘11110001’;

Decisions and loops
If-then-else. The basic syntax for a simple if statement is as follows:

if (condition) then
      ... statements
end if;

The condition is a Boolean expression, of the for m a b or a b. Note that the comparison operator for equality is a single , not to be confused with the double used in some programming languages. For example, if two signals are equal, then set an output high would be written in VHDL as:

if ( a = b ) then
    out1 <= ‘1’;
end if;

If the decision needs to have both the if and else options, then the statement is extended as follows:

if (condition) then
    ... statements
else
    ... statements
end if;

So in the previous example, we could add the else statements as follows:

if ( a = b ) then
     out1 <= ‘1’;
else
     out1 <= ‘0’;
end if;

And finally, multiple if conditions can be implemented using the general form:

if (condition1) then
    ... statements
elsif (condition2)
    ... statements
... more elsif conditions & statements
else
    ... statements
end if; 

With an example:

if (a > 10) then
     out1 <= ‘1’;
elsif (a > 5) then
     out1 <= ‘0’;
else
     out1 <= ‘1’;
end if;

Case. As we have seen with the IF statement, it is relatively simple to define multiple conditions, but it becomes a little cumbersome, and so the case statement offers a simple approach to branching, without having to use Boolean conditions in every case.

This is especially useful for defining state diagrams or for specific transitions between states using enumerated types. An example of a case statement is:

case testvariable is
    when 1 =>
      out1 <= ‘1’;
    when 2 =>
      out2 <= ‘1’;
    when 3 =>
      out3 <= ‘1’;
end case;

This can be extended to a range of values, not just a single value :

case test is
    when 0 to 4 => out1 <= ‘1’;

It is also possible to use Boolean conditions and equations. In the case of the default option (i.e. when none of the conditions have been met), then the term when others can be used:

case test is
     when 0 => out1 <= ‘1’;
     when others => out1 <= ‘0’;
end case;

For. The most basic loop in VHDL is the FOR loop. This is a loop that executes a fixed number of times. The basic syntax for the FOR loop is shown below:

for loopvar in start to finish loop
     ... loop statements
end loop;

It is also possible to execute a loop that counts down rather than up, and the general form of this loop is:

for loopvar in start downto finish loop
     ... loop statements
end loop;

A typical example of a for loop would be to pack an array with values bit by bit, for example:

signal a : std_logic_vector(7 downto 0);
for i in 0 to 7 loop
     a(i) <= ‘1’;
end loop;

While and loop. Both the while and loop loops have an in-determinant number of loops, compared to the fixed number of loops in a FOR loop and as such are usually not able to be synthesized. For FPGA design, they are not feasible as they will usually cause an error when the VHDL model is compiled by the synthesis software.

Exit. The exit command allows a FOR loop to be exited completely. This can be useful when a condition is reached and the remainder of the loop is no longer required. The syntax for the exit command is shown below:

for i in 0 to 7 loop
    if ( i = 4 ) then
        exit;
    endif;
endloop;

Next. The next command allows a FOR loop iteration to be exited, this is slightly different to the exit command in that the cur rent iteration is exited, but the overall loop continues onto the next iteration.

This can be useful when a condition is reached and the remainder of the iteration is no longer required. An example for the next command is shown below:

for i in 0 to 7 loop
    if ( i = 4 ) then
       next;
    endif;
endloop;

To read Part 2, go to: More essential VHDL commands.
To read Part 3, go to:  Building ALU logic and FSMs.
To read more by Peter Wilson, go to: A simple VGA interface

Used with permission from Newnes, a division of Elsevier. Copyright 2007, from “Design Recipies for FPGAs,” by Peter Wilson. For more information about this title and other similar books, please visit www.elsevierdirect.com.

Dr. Peter Wilson has worked for many years as a senior design engineer in the electronics industry with Ferranti plc and as an EDA technical specialist with Analogy Inc. before joining the Department of Electronics and Computer Science at the University of Southampton, U.K., where he is senior lecturer in Electronics. He is also a consultant in various aspects of embedded systems design, including design and modeling with VHDL, Verilog, Verilog-AMS and VHDL-AMS.