A guide to VHDL for embedded software developers: Part 1 – Essential commands

Peter Wilson

July 19, 2011

Peter WilsonJuly 19, 2011

Editor’s Note: In this series of articles based on his book – Design Recipes for FPGAs – Peter Wilson provides a basic quick overview of VHDL (VHSIC hardware description language) followed by examples of its use in describing - in HDL code form - functions familiar to most embedded software developers such as arithmetic logic units (ALUs) and finite state machines (FSMs). It is not intended as a comprehensive VHDL reference. For that, he recommends “Digital System Design with VHDL,” by Mark Zwolinski; ”VHDL: Analysis and modeling of digital systems,” by Zainalabedin Navabi or “Designer’s Guide to VHDL” by Peter Ashenden.

This series of articles is designed to give concise and useful summary information on important language constructs and usage in VHDL – helpful and easy to use, but not necessarily complete.

It will introduce the key concepts in VHDL and the important syntax required for most VHDL designs, particularly with reference to Field Programmable Gate Arrays (FPGAs).

In most cases, the decision to use VHDL over other languages such as Verilog or SystemC, will have less to do with designer choice, and more to do with software availability and company decisions. Over the last decade or so, a ‘war of words’ has raged between the VHDL and Verilog communities about which is the best language, and in most cases it is completely pointless as the issue is more about design than syntax.

There are numerous differences in the detail between VHDL and Verilog, but the fundamental philosophical difference historically has been the design context of the two languages.

Verilog has come from a ‘bottom-up’ tradition and has been heavily used by the IC industry for cell-based design, whereas the VHDL language has been developed much more from a ‘topdown’ perspective.

Of course, these are generalizations and largely out of date in a modern context, but the result is clearly seen in the basic syntax and methods of the two languages. Without descending into a minute dissection of the differences between Verilog and VHDL one important advantage of VHDL is the ability to use multiple levels of model with different architectures.

This is not unique to VHDL, and in fact Verilog does have the concept of different behavior in a single ‘module’; however, it is explicitly defined in VHDL and is extremely useful in putting together practical multi-level designs in VHDL.

The division of a model into its interface part (the ‘entity’ in VHDL) and the behavior part (the ‘architecture’ in VHDL) is an incredibly practical approach for modeling multiple behavior for a single interface and makes model exchange and multiple implementations straightforward.

The remainder of the first part in this series will describe the key parts of VHDL, starting with the definition of a basic model structure using entities and architectures, discuss the important variable types, review the methods of encapsulating concur rent, sequential and hierarchical behavior and finally introduce the important fundamental data types required in VHDL.

Entity: model interface
Entity definition. The entity defines how a design element described in VHDL connects to other VHDL models and also defines the name of the model. The entity also allows the definition of any parameters that are to be passed into the model using hierarchy. The basic template for an entity is as follows:

entity is
....
entity ;

If the entity has the name ‘test’, then the entity template could be either:

entity test is
end entity test;

OR:

entity test is
end test;

Ports. The method of connecting entities together is using PORTS. These are defined in the entity using the following method:

port
(
...list of port declarations...
);

The port declaration defines the type of connection and direction where appropriate. For example, the port declaration for an input bit called in1 would be as follows:

in1 : in bit;

And if the model had two inputs (in1 and in2) of type bit and a single output (out1) of type bit, then the declaration of the ports would be as follows:

port (
    in1, in2 : in bit;
    out1 : out bit
);

As the connection points between entities are effectively the same as those inter-process connections, they are effectively signals and can be used as such within the VHDL of the model.

Generics. If the model has a parameter, then this is defined using generics. The general declaration of generics is shown below:

generic (
...list of generic declarations...
);

In the case of generics, the declaration is similar to that of a constant with the for m as shown below:

param1 : integer := 4;

Taking an example of a model that had two generics (gain (integer) and time_delay (time)), they could be defined in the entity as follows:

generic (
    gain : integer := 4;
    time_delay : time = 10 ns
);

Constants. It is also possible to include model specific constants in the entity using the standard declaration of constants method previously described, for example:

constant : rpullup : real := 1000.0;

Entity examples. To illustrate a complete entity, we can bring together the ports and generics examples previously and construct the complete entity for this example:

entity test is
    port (
       in1, in2 : in bit;
       out1 : out bit
    );
    generic (
       gain : integer := 4;
       time_delay : time := 10 ns
    );
    constant : rpullup : real := 1000.0;
end entity test;

< Previous
Page 1 of 3
Next >

Loading comments...

Most Commented

  • Currently no items

Parts Search Datasheets.com

KNOWLEDGE CENTER