Design Con 2015

Efficient I2C Bus debug using Mixed Signal Oscilloscopes

Dave Pereles, Tektronix

October 07, 2012

Dave Pereles, TektronixOctober 07, 2012

Version 4.0 of the Inter-IC (I2C) bus is widely used in embedded system designs, and has been used for communications and control applications in thousands of integrated circuits.

What’s also still widely used is manual measurement and debug, in part because engineers assume that since I2C has been around for a long time, there’s little to go wrong. The trouble comes when there’s a need to trigger bus commands using manual decode.

I2, I2C, or “I squared C”, stands for Inter-Integrated Circuit. It was originally developed by Philips Semiconductor in the early 1980s to provide a low-cost way of connecting controllers to peripheral chips, and has since evolved into a worldwide standard for communication between devices in embedded systems.

The simple two-wire design has found its way into an extensive cross section of chips including I/O, A/Ds, D/As, temperature sensors, microcontrollers and microprocessors from numerous leading chipmakers including Analog Devices, Atmel, Cyprus, Freescale, Infineon, Intel, Maxim, Microchip, NXP, Silicon Labs, ST Microelectronics, Texas Instruments, Xicor, and many others.

I2’s physical two-wire interface (Figure 1) consists of bi-directional serial clock (SCL) and data (SDA) lines. I2C supports multiple masters and slaves on the bus, but only one master may be active at a time. Any I2 device can be attached to the bus allowing any master device to exchange information with a slave device. Each device is recognized by a unique address. A device can operate as either a transmitter or a receiver.


Click on image to enlarge.

Figure 1. The standard I2 message structure.

Initially, I2 only used 7-bit addresses, but evolved to allow 10-bit addressing as well. Now four bit rates are supported: 100 kb/s (standard mode), 400 kb/s (fast mode), and 3.4 Mb/s (high-speed mode) and 5 Mb/s (ultra-fast mode). The maximum number of devices is determined by a maximum capacitance of 400 pF or roughly 20-30 devices.

Released in February 2012, version 4.0 of the I2 specification adds the 5 Mb/s mode for new serial data and clock lines using push-pull logic and adds an assigned manufacturer identification table. The I2 standard specifies the following format for messages:

* Start - indicates the master device is taking control of the bus and that a message will follow.
* Address - a 7 or 10 bit number representing the address of the device that will either be read from or written to.
* R/W Bit - one bit indicating if the data will be read from or written to the slave device.
* Ack - one bit from the slave device acknowledging the master’s actions. Usually each address and data byte has an acknowledge, but not always.
* Data - an integer number of bytes read from or written to the device.
* Stop - indicates the message is complete and the master has released the bus.

Since I2 uses separate clock and data lines, it is possible to use the clock as a reference point and manually decode the data line. However, the engineer needs to find the start of the message (data going low while the clock is high), manually inspect and write down the data value on every rising edge of the clock, and then organize the bits into the message structure.

Using a quick reference guide like that shown in Figure 2, it can easily take a couple of minutes of work just to decode a single message and in a long acquisition and there’s no way of knowing if it’s the message you’re looking for until you’ve decoded it. If it’s not, then you need to start the tedious and error prone decoding process over again until you find the right message.

It would be nice to just trigger on the correct message content, however the state and pattern triggers traditionally used for years on scopes and logic analyzers won’t do you any good here. They are designed to look at a pattern occurring at the same time across multiple channels. To work on a serial bus, their trigger engines would need to be tens to hundreds of states deep (one state per bit).


Click on image to enlarge.

Figure 2. The reference guide is used to decode I2 packets manually, a time consuming process.

Fortunately, there is a better way. With the appropriate serial triggering and analysis application module, a mixed signal oscilloscope becomes a powerful tool for embedded system designers working with I2 buses. A typical mixed signal oscilloscope includes 4 analog channels and up to 16 digital channels, all fully time correlated.

By defining which channels clock and data are on, along with the thresholds used to determine logic ones and zeroes, you can quickly enable an MSO to understand the protocol being transmitted across the bus.

With this knowledge, the oscilloscope can trigger on any specified message-level information and then decode the resulting acquisition into meaningful, easily interpreted results. Gone are the days of edge triggering, hoping the oscilloscope acquired the event of interest, and then manually decoding message after message while looking for the problem.

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