Reducing tester-based silicon debug effort & time: Part 2 – A check-list of best practices

Neha Srivastava, Nitin Goel, and Aashish Mittal - Freescale Semiconductor

January 8, 2013

Neha Srivastava, Nitin Goel, and Aashish Mittal - Freescale Semiconductor

Must-do practice #9
Care must be taken to ensure that no valid pad can be designated x/z for any portion of the VCD for the tester pattern. Also all unused pads must be masked off in the VCD.

Issue Analysis For patterns with analog behaviors and analog pads being tested, the unused pads should be masked in the resimulation environment. If they are not, they get looped back and thus a high-z state occurs on these pads for some time duration due to delay in do-> pad path. This leads to x corruption in design.

Also all valid pads being probed or driven in the VCD must never be allowed to be x/z for any portion of time in the VCD since that again can cause the same issue as above.

Solution Automatic script analysis must be enabled to find out all pads with x/z state, and either mask them off if they are unused or drive them with safe value when not driven actively.

Other important VFT practices
Some other practices that ensure smooth porting and direct mapping of the simulation behavior of the VCD/patterns with the behavior observed on tester include:

• Provide the maximum possible time for analog modules to get stable and provide their status (for example, the status from the voltage regulator for Power-on-reset de-assertion) and also for the maximum possible scanning time for initialization data from on-chip flash, etc., at startup should be considered. Accordingly, you should delay programming in the VCD, no matter what time factor is visible during simulation due to usage of behavioral models.
• Make sure the freezing of the main clock (for example, before taking system to reset) and restarting (once we are out of reset) of the main clock on which the VCD is based are done in exact multiples of the cycle period, never on a half clock period , (i.e., the time from the positive edge of clock before freezing), and on the positive edge of clock on restarting using an integral multiple of the clock period. This latter maintains cycle synchronization which aids smother operation on tester (since cycle based nature needs to be maintained).
• To finish off the testcase execution in a synchronized manner, in case the pattern expects some return value (to signal pass/fail) from the core side code sent out on the same pads as those used for downloading the code, probed by the verilog component. Then this probing needs to be enabled only after the download has finished since otherwise random code-data being downloaded can trigger off a false pass/fail and lead to a testcase finish before actual code execution even starts. 
• Test mode entry schemes and their startup and shutdown sequences must be developed such that the VCDs are compliant for running back-to-back on tester. Doing this will enable faster execution on the tester by trimming the start and end of the VCDs and joining them end-to-end, running one after the other, without needing a power-off/on in between.
• If the design is such that the peripheral clocks are disabled by default during and after power-up, then for each test-case you should start with a clock enabling macro to enable the clock of each module. Otherwise, the pattern may get stuck while accessing register of modules whose clocks are not even enabled. 
• VCD should not have any internal signal forcing/probing or any hard delays.
• As far as possible, the cache should not be enabled by default since it can cause unpredictable failures, making debugging difficult. 
• As far as possible and as allowed by memory constraints, hex patterns should always be loaded into the backup-system RAM (which is active even in low-power modes) so that all patterns can be tuned to run into low-power modes if required.
• The source code for the tester should be highly optimized to reduce memory and time during download. 
• The pads being used to signal some output on tester should always have their slew rates programmed to values that ensure their fastest behavior. Otherwise you may end up in a loop, debugging some unnecessary slow pad issue.
• For a signature on Tester cases, no pad should be toggling at the frequency of the input clock of the pattern. In other words , the input clock should be the fastest clock in the VCD (apart from the PLL /DDR output clocks) to ensure proper sampling of all transitions.
• INFO/DEBUG statements should never be used in the Tester patterns. Their use unnecessarily increases the code length. Their use also leads to porthole issues. Not only does this put a strain on the already limited memory on the tester and lead to unnecessary debug ( such as in case the porthole locations), the scheme doesn’t work reliably when implemented in silicon.

A stitch in time saves nine
These best-practice recommendations are the result of insights gained by generating the VFT testbench infrastructure, creating and simulating the tester patterns, and debugging the failures observed in simulation as well as on silicon.

Through the use of such "learning from experience" procedures, we've saved unnecessary iterations of simulation pass/silicon failure pattern/infrastructure modification for most of the patterns. Instead, they are caught early on in simulation itself and result in the delivery of pattern VCDs which are correct by construction.

This has also reduced functional tester pattern bring-up time, as well as tester time and debug effort. This combination ultimately brings down the overall cost of chip design and test but at the same time results in higher quality performance at customer end. We consider these techniques generic and capable of ensuring an improvement in overall efficiency of VFT engineers.

Part 1: Testing modes

Neha Srivastava is a lead design engineer at Freescale Semiconductors (Noida, India Design Centre), working in the Automotive and Industrial Solution Group (AISG) for over 5 years. She has a Bachelor of Engineering (B.E.) degree from Birla Institute of Technology and has worked on multiple SoCs in front-end verification and Verification for Testing domain with the areas of interest being low power designs, safety architectures, and high performance systems. She can be reached at Neha.Srivastava@freescale.com.

Aashish Mittal is a principle design engineer at Freescale Semiconductors (Noida, India Design Centre), working in the Automotive and Industrial Solution Group(AISG) for over 12 years. He has a Master of Technology from Banaras Hindu University and has worked on multiple SoCs in front-end verification, Testbench Integration and Verification for Testing domain with the areas of interest being dual core, security, debug and low power architecture. He can be reached at aashish@freescale.com.

Nitin Goel is senior design engineer at Freescale Semiconductor India Pvt. Ltd , working in the Automotive Microcontroller Group (AMCG) for over 6 years . He graduated from Netaji Subhash Institute Of Technology, Delhi in 2006. Since, then he has been working in Frontend verification domain. Along with experience in IP Level, SoC Level, and Core verification , he has been working in Tester pattern development and debugging.