Mixed signal verification of Sigma Delta ADCs in an SoCIn this article we describe a mixed signal verification method for doing Signal Delta dynamic tests in a system-on-chip (SoC) environment. We detail the methods for verifying the ADC in an RTL+SPICE or RTL+VAMS (Verilog AMS) based abstraction of the SoC, where the analog part of the design has an electrical based modeling (VAMS/SPICE). (To review the basics of sigma delta ADCs, read The basics of sigma delta analog-to-digital converters.)
To calculate the signal and the noise frequency that can be used as a stimulus for the ADC Verification in the proposed Mixed Mode Environment, we present a simple formula that can be applied on any ADC Subsystem. This stimulus can then be used on the ADC channels to do noise rejection checks and observe the Clock Jitter impact on SNR when using various clock sources such as PLL, IRC etc. The described method equips the mixed signal SoC designer to verify ADC Performance across different possible combinations of SoC modes of operation.
Traditional verification methods rely on digital/analog measurement accuracy and do not find out parameters like SNR/ENOB. The proposed method and flow solves this problem by giving a calculated stimulus that not only tests the modulator (in case of Sigma Delta ADC), but also tests the performance of the decimation filter. ADC dynamic characteristics are crucial for many markets, e.g. metering, motor control, etc. At Present, SoC teams rarely check these with SoC network of data converter and its IO/muxing interface.
The second part of the article describes how to qualitatively analyze dynamic characteristics of Data Converters. This process enhances the verification environment with regression capability, which shows PASS/FAIL at the end of the test case considering the values of certain important results.
Signal and noise frequency calculation
With reference to Figure 1, sampled data is assumed to be repetitive while calculating the fast fourier transform (FFT) where:
- Fi = Input Frequency
- Ts = sampling time
- Nsa = No.of samples (2n) n = 1,2,3…..
The relation shown here should hold true to calculate the best signal to noise ratio (SNR).
Ts x Nsa = n(1/F1)
Figure 1: Signal to noise sampling
The best approach is to fix the number of samples (at which point FFT is to be performed); then given the sampling time Ts , apply the corresponding frequency Fi to the input or vice versa.
A data converter is a low pass filter, let's say its cut-off frequency is Fc. If the signal frequency is lower than Fc then it gets converted and displayed at the output; if a signal has a frequency greater than Fc then ADC does not convert those components. This is the basis of this design solution.
Example of a data converter with following specifications:
- Differential signal dynamic range as per IP specs = +/-250mV
- Output digital bus width = 24
- Clock frequency = 6.14Mhz(163ns)
- OSR (over sampling ratio) supported = 64
- Single data generation time (avg with 64 samples) = 163ns*64 = 10.43us
128 samples would take 10.43us*128=1.33504ms ( 749.04Hz)
As per Nyquist criteria , we need two samples in one cycle to regenerate the signal, hence signal max frequency (noise threshold) = 1e06/(2*10.43)Hz = 47.9Khz.
Noise source can be interleaved on signal source to generate Dynamic I/P signal for mixed mode simulations. Note: For other data converter systems OSR = 1 can be assumed; the rest of the calculation remains the same.
Figure 2: When the noise frequency is kept less than Nyquist frequency, the noise is reflected at the output. Hence, it is suggested that the noise frequency be selected at least equal to or greater than Nyquist frequency.
Modes of SoC operation
The proposed verification methodology can completely verify the working of a data converter subsystem in either the normal run mode or the low power mode. Figure 3 shows an example of one such subsystem working in normal run mode.
Click on image to enlarge.
Figure 3: Results indicating noise rejection at the output of an ADC
Using this method in low power modes, where the data converter runs on low power with low quality clock source, we can say how the jitter on the clock can be seen at the output by observing SNR and dynamic range.
Mixed mode verification as opposed to simulating the entire design in transistor level form (SPICE) gives more coverage in multiple functionalities, clock sources, and modes of operation. For verifying, the present SoC flows use the decimator and receiver by modeling the modulator in synthesizable logic. This may not be able to check the behaviors due to bad integration of modulator.
This is a simple and realistic way to predict dynamic behavior of the data converter through SoC mixed mode simulations where the impact due to SoC integration--multiplexing structure, loading, routing package and boards--can be estimated prior to silicon reaching customers
Qualitatively analyze dynamic characteristics of data converters
A parameterized Verilog-AMS SNR/ENOB and dynamic range calculator can be used to test different ADC architectures(SAR,SD-ADC). The data from these VAMS models are compared against MATLAB for correlation.
Using this method, one can do noise rejection checks, see the clock jitter impact on SNR across different SoC modes of operation (PLL,IRC, etc), perform dynamic range check through VAMS monitor to identify signal attenuation due to bad IO muxing, high source impedance, and sampling issues at high clock speeds.
Dynamic checks for data converters are done in the post silicon phase, where the dynamic parameters are calculated. These parameters, if having a lower value than expected, can reveal which blocks in a data converter subsystem are the culprits. In this way the dynamic checks for data converters can be done and issues can be identified early in the pre-silicon simulation phase.
With this method, impact of noise on input can be checked and data converter characteristics can be estimated against poor signal quality. Impact of clock jitter can be verified in the simulations to measure impact in SNDR/SNR.
A VAMS-based model for SNDR/SNR calculation eliminates MATLAB usage, which is encouraged due to limited licenses and cost. Also, data need not be manually entered as when included in the testbench, the VAMS Model collects the data. This is not possible in MATLAB for analysis, i.e., the proposed flow works simultaneous with data collection without MATLAB.
MATLAB is the standard tool for performing the analysis for dynamic performance, but licensing cost is a concern. Our proposed flow not only eliminates the usage of MATLAB but eases the calculation of the dynamic parameters. It also performs noise rejection/tolerance, which is not checked in pure digital verification.
Such a verification methodology can be used to set up a regression environment, thereby ensuring higher coverage in less time.
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