3D TSV Test: ATE challenges and potential solutions

Ben, Scott, Karen, Andy, Robert, and Erik, Verigy

October 24, 2011

Ben, Scott, Karen, Andy, Robert, and Erik, Verigy

Introduction
The 3D TSV revolution is happening! After a slow start, the solution for increased circuit density, lower power consumption and improved bandwidth appears to be on its way for adoption in the industry. There is a strong emerging community of test engineers addressing various test challenges [1]-[4] as well as various emerging standards [14], [15]. Significant progress has been made in mapping out the problems and developing various solutions. However, there is still significant uncertainty in the industry, especially in certain areas such as wide-IO memory integration.

In a recent poll at the SEMI/IEEE International Workshop on ATE: ATE Vision 2020, 70% of the audience expressed uncertainty on 3D TSV test methodologies. 3D TSV disruption causes problems that either relate to acceleration of the already foreseen heterogeneous integration roadmap to unique new problems related to 3D.

The first problems make certain test solutions uniquely suitable for 3D even-though the solutions in isolation are not necessary specifically developed for 3D. Moreover, solutions range can be grouped in existing solutions applied to new problems (such as test insertion algorithms to minimize the number of TSVs that need dedicated test pads) or new solutions (such as partial stack test equipment or probing for microbonds).

This paper presents some of the 3D TSV test challenges and proposes potential solutions for them. It also attempts to clarify some of the 3D TSV test myths and misconceptions. The final section lists some of the challenges the industry is working on to allow full 3D TSV adoption. The objective of the paper is not to present a full set of 3DTSV test solutions, but to give a flavor of some of the problems and potential solution directions. Some of the solutions discussed are commercially available while others require more research and development work.

Motivation
One of the major motivations for new test methodologies and equipment geared towards 3D TSV test stems from a significant increase in the number of potential defects as well as the introduction of new defect types. Figure 1 is a summary of the types of defects introduced by TSVs and their failure modes [5], [6]. For instance, there are defects related to the bonding process that result in shorts and opens. Defects in TSVs due to the manufacturing process like micro-voids and pinholes can affect the AC performance of the circuit or create shorts to the substrate. If materials with widely different thermal expansion coefficients are used, cracks in the TSV insulative liner result, followed by reliability problems. Testing for some of these defects requires highly sensitive and accurate measurements. Given the expected large number of TSVs to be implemented, highly parallel measurements will also be required.


Challenge: Test flow complexity and cost optimization
The stacking of different die of different quality with different test requirements using multiple test insertions significantly challenges our existing economic models to minimize test cost. For example, for some devices it might be suitable to test the partial stack whereas for others the costs would be prohibitive.

Solution component: 3D TSV test cost model
There is a need for novel test economic models to optimize the significantly expanding set of tradeoff dimensions. Therefore, we have developed a cost model that takes various factors into account, including: pre-bond die test, the cost of rejected stacks, and the cost of final stack test. We assumed there is no partial stack test so that the relationship between die pre-bond and final test is better reflected by the economic model. We use the cost model to find the optimal test assignment between pre-bond and final test from a cost perspective. We have applied the model to representative 3D stacks where we varied the number of die in each 3D stack from 2 to 10 in increments of 2 die. The die are all the same type, and therefore have the same cost, and cost of test. The results are shown in Figure 2.


By looking carefully at the graphs in Figure 2 one can conclude the following:

• Each graph has a minima where the percentages of pre-bond and final test costs are optimized,
• To the right of the minima, test cost increases mainly due to final test,
• To the left of the minima, test cost increases mainly due to pre-bond test,
• The cost of test increases as the number of die increases,
• The more die in the stack, the more individual die test is required.

In various technical meetings and conferences the need for KGD (Known Good Die) is discussed extensively as a precondition to achieve the required 3D stack yields. At the same time and in contrast, there are groups that feel the traditional wafer test methodologies are acceptable. The economic model demonstrates that neither position is correct for all cases and that each case needs to be analyzed in order to identify the optimal test approach from a test cost perspective.

Challenge: Sensitive instruments with high parallelism for some defects
As mentioned above, some new defects introduced by TSVs include pinholes in the TSV insulative liner, which lead to leakage currents. These currents are in the 100s of picoAmperes and require very sensitive and accurate measuring instrumentation. Given that the number of TSVs in a die is expected to be large, parallel measurements are required to optimize test throughput (at the least during characterization). There are instruments capable of measuring currents in the femto-Amp range, but they lack the parallelism and sophisticated digital test capabilities of traditional ATE. Typical ATE parametric measurement capabilities are either not truly parallel or not sensitive enough.

Solution component: PicoAmp meter
Verigy has developed an instrument with the required characteristics suitable for TSV parasitic current measurements called the picoAmp meter. The primitive is a single board with 2 channels. Four channel boards are integrated into a motherboard resulting in 8 channels in a picoAmp meter module as illustrated in Figure 3.


There are multiple sources of error that can corrupt measurements when measuring currents in the pico-Ampere region like, for instance, the parasitic leakage in coaxial cables and noise generated from the spurious charges that can develop in a cable when the guard metal rubs against the insulator (e.g., through vibration). By judiciously using special circuit techniques and the right materials, these, and other challenges, can be addressed. Parallelism can be achieved by integrating the required number of picoAmp meter modules into the test system. By multiplexing the possible inputs to the tester channels, functionality other than picoAmp measurements is possible, for instance high speed digital test or standard V/I parametric measurements.

Challenge: Improved wafer test
One conclusion we obtained from the cost model described above was that an increasing number of die in a 3D stack will require better test at the wafer level. High performance test usually associated with final test will now be required at wafer test. Improving wafer test performance requires improved signal integrity.

Solution component: Direct Probe
Verigy’s solution for this problem is called Direct Probe and is illustrated in Figure 4a. Direct Probe eliminates two of the four transitions in the signal path from the tester channel to the DUT. This results in fewer undesired signal reflections because of the lower number of impedance changes, and in a more reproducible and regular signal path impedance.


Figure 4b shows measurements for a typical Pseudo Random Binary Sequence use to measure the Bit Error Rate in the line.


As seen from these eye diagrams, the signal integrity is very much improved. Therefore, a higher performance wafer test can be implemented by using Direct Probe.

Solution component: TSV SpeedScan technique
Voids or partially filled TSV structures can result in variations in path delays with temperature, leading to failures [7]. By applying AC/At-Speed scan tests at different temperature (e.g., normal temperature and high temperature) we can stress the device to gain additional test coverage. We identify paths through TSVs that show an increase/decrease in the passing frequency at high temperature when compared with the vast majority of other paths (i.e., we’re identifying the statistical significant outliers). Based on these results, potential issues can be identified by comparing the locations of the failures to the results of timing analysis.

Challenge: TSV yield improvement
Another challenge is presented by the TSV quality. Figure 5a shows the die yield as a function of the percentage of good TSVs in the same die, for different numbers of die. Assume a manufacturing process gives 96% good TSV in a die. Die with 100 TSVs will yield 4% – very poorly. Assume further that the manufacturing process is improved to yield 99.5% good TSV. The die yield will go from 4% to 64% – a marked improvement. However, for die with five times more TSVs, the 99.5% TSV yield translates into a 10% die yield, which is, again very poor. This example considers a relatively small number of die to illustrate the challenge.


Consider the graph shown in Figure 5b where a wide range for the number of TSVs is considered. Starting from 10, it can be seen that the requirement for very high quality TSVs goes up very quickly. Will the manufacturing process be able to produce such quality TSVs to accommodate the ever increasing number of TSVs in a cost effective manner?


Solution component: Design for repair-ability and RA ATE
One solution is building redundant TSVs into the circuit so that when a TSV fails it can be bypassed by a redundant one. For instance, a simple example reported in the literature considers including a redundant TSV for every 4 TSVs in the circuit as illustrated in Figure 6a [13]. We expect that, similar to memories, including redundant TSVs and its allocation for repair will become a design competency and it will require algorithms that optimize the allocation of redundant TSVs for repair.


From a chip manufacturer perspective, developing and controlling these algorithms will become a competitive advantage. Therefore, an open ATE Redundancy Analysis and Repair Platform like the one illustrated in Figure 6b becomes a requirement. Note that the same RA Platform can be used for Redundancy Analysis and Repair of the memory cubes to improve stack yield. Because of the third dimension in the memory cube there are new opportunities for improved algorithms and solution.


Challenge: Power and thermal management
3D structures bring with them higher densities, greater functionality, and faster clock rates. All of which mean greater local power dissipation. Power dissipation is three times higher in 3D stacks than in a 2D IC [16]. Elevated temperatures contribute to lower semiconductor reliability. Thermal management becomes key to 3D structure reliability. It's no longer sufficient to simply add "a bigger fan" as a downstream fix for thermal problems.

3D chips will have so many transistors that, from a thermal perspective, it is impractical to supply power to all of them at the same time for fear of melting silicon in “hot spots” of the design. Hence some of the transistors must be left unpowered – or “dark” in industry vernacular – while the others are working. The phenomenon is known as “dark silicon.” Management of the active and inactive sections of 3D layers complicates the test process.

Solution component: Concurrent test
Verigy’s concurrent test architecture partly addresses these concerns by partitioning the tester’s resources into what could be considered separate independent testers, or ports. Verigy’s port partitioning is highly granular and with 256 available, one can be configured to test each dynamically powered sub function of each die in the 3D stack. By managing test activities on these ports during production test, thermal issues are managed dynamically by the tester itself or through communication from the device. There are interesting new dimension of scheduling such as power constraints and cross talk constraints. Moreover sharing of resources can happen across partial stack multi-site test.

Challenge: 3D TSV test program collaboration and configuration management
Production test of 3D chips designs will require cumulative cooperation of many test engineers. Teams responsible for testing one layer must collaborate with the members of teams responsible for other layers. Without test program IP reusability, sharing, and communication across these teams, test coverage mismatch will occur at stack layer integration time.

Solution component: Smart test program management
Verigy’s Smart Test Program Manager helps mitigate some of these logistical concerns. Like other software version control products (Clearcase, Subversion, CVS) Smart Test Program Manager erects a collaborative environment which allows test program check in/out, IP reuse, and integration. What’s more, features of it allow for direct translation of design data base input/output data for production yield feedback purposes. The complex landscape of 3D layer test program management is illuminated with one tool and eliminates the likelihood of fault grade or communication holes between development teams.

3D TSV test challenges with solutions under development
This section describes some of the 3D TSV test challenges being currently addressed by the industry.

• The need for advanced 3D TSV Diagnostics Software – 3DTSV causes new defect mechanisms and it is important to have the right set of SW tools to achieve 3DTSV yield learning. These tools will allow the analysis of the data resulting from testing 3D devices, and the translation of this data into information to guide process changes leading to yield improvement.
• EDA tool enhancements for 3D TSV test – EDA Tools need to be integrated with test strategies and solutions so that the design and design for test of 3D TSV devices can occur concurrently as it happens today for 2D devices.
• The need for 3D TSV DFT Standards – Standards are powerful tools that help accelerate the adoption and maturation of a new technology [12]. Take for instance the 1149.1 Boundary Scan standard as applied to PCB/PCA testing. The IEEE P1838 Working Group is currently working on developing a standard to help address the 3D TSV test challenges by providing amongst other features, a standardized access mechanism to test the 3D stack and its components at different stages during its life cycle. Another example is the JEDEC Low Power Memories Subcommittee (JC-42.6) developing standards for Wide I/O Mobile Memory with TSV interconnect stacked on a System on a Chip (SoC) Application Processors.
• New IC Design Architectures Enabled by 3D TSV – The first generation of 3D TSV chips does not distribute logic functions across various levels to optimize the design performance to the fullest extent possible. Once EDA tools fully incorporate the new design opportunities 3D offers at a very fine- granularity, many new architectural options are enabled with many new test challenges. For example, this can lead to circuits where the clock tree does not exist in the circuit-under-test but in another layer rendering the circuit un-testable using traditional approaches. Another example would be: assume one die in a 3D circuit-stack contains a processing unit and memory located in different die. how do you test the processor unit alone, in mission mode, using a conventional ATE system? [8] One alternative would be to implement a “virtual emulation” using existing ATE HW and SW. This approach, however, suffers from excessive latency which renders it unfeasible. Protocol-aware ATE, specifically, ATE able to work “natively” in “memory emulation” mode would be able to overcome the main limitations in traditional ATE systems, including latency, and fully test the processor unit in isolation [9], [10].
• 3D TSV Probing – The forecasted pitch and TSV sizes are in the order of tens to a few microns. Challenges arise in the area of the probe-to-TSV contact resistance, probe compliance required to guarantee an average contact force across the probe face, and force distribution across an array of probe tips. Potential pad damage has been identified as a major risk and has been given a lot of attention in the recent past. More recently, reported pad damage results are encouraging and appear to indicate that the damage cause by probing will not preclude its use [11].
• 3D TSV Partial Stack Test – Depending on the quality requirements, the number of die in a stack and cost, it may make sense for certain applications to test a partially constructed 3D stack. There are two approaches to performing partial stack test: (a) Bottom partial stack test: the probe card connects to the bottom die. The concern of this approach is signal integrity and power integrity at the top level die; (b) Top partial stack test: the probe card always connects to the top die. A challenge arises if the stack has a structure that is not leveled (also known as 2.5D).

Conclusion
3D TSV increases circuit density, lowers power consumption, and improves bandwidth. It’s very clear that it is on its way for adoption in the industry. The focus in the industry is somewhat shifting from obtaining the necessary test capability to cost optimization.

A lot of challenges have been addressed with innovative solutions and this paper suggests that a set of different solutions to point problems, some of which with benefits beyond 3D TSV test, combined make up for a very powerful solution for 3D TSV test. Moreover, there are specific solutions that are uniquely geared towards 3D TSV test. Finally, some of the remaining test challenges for full 3D TSV adoption were listed.

About the authors
Ben Rogel-Favila – Ben is Program Manager for Verigy Labs and he is currently leading Verigy’s 3D TSV research initiative. Ben has over 20 years of experience in the semiconductor test industry. Ben holds a PhD degree from Imperial College, London.

Scott Chesnut – Scott has been an apps engineer for 28 yrs. He works closely with over 34 semiconductor companies, hundreds of test, product, and design engineers as a test solution developer in the areas of high speed digital, mixed signal/baseband, and RF applications. His documentation of such is found as reference material throughout Verigy’s product portfolio and serves to complete the more seamless transfer of new products from the R&D laboratory to customers and field AE.

Karen Herbstman – Karen has worked as a Semiconductor Test Account Manager since Verigy spun off from Agilent in 2006.  Prior to that, Karen was an Account Manager at Agilent Technologies and sales representative at Hewlett Packard for various accounts for both semiconductor test and bench top test instruments.  Karen holds an EE degree from Cornell University.

Andrew Niemic – Andy is Software Architect for Verigy.  His expertise includes mathematics and redundant analysis on DRAM and FLASH. Andy holds degrees in MSEE and MS in Mathematics from Arizona State University.

Robert Smith – Bob is a Senior Applications Engineer at Verigy-Advantest and supports Low current DC measurements, 3D and TSV testing applications. His background includes working as an applications engineer on RCL Impedance instruments, DC parametric, digital, analog power, and analog mixed signals tester systems at Hewlett Packard and Agilent.  He originally came from AT&T Bell Laboratories where he worked doing simulation, design and testing of state of the art ICs.  His education background is a B.S. in Engineering and an MS in Computer Science in circuit and system simulation.

Erik Volkerink – Erik is the CTO of Verigy. He directs Verigy’s R&D infrastructure programs including long-term research and intellectual property, and directs a funnel of strategic marketing and engineering initiatives in core, adjacent, and disruptive markets. He’s Founder and General Chair of ATE Vision 2020, Program Chair of the International Test Conference, and Cost of Test Section Chair of the ITRS. He’s recipient of the Best Paper Award of the CPA conference, Best Paper Award Nomination of the Design  Automation Conference, and Most Successful IEEE Event Award. He obtained a PhD from Stanford University and a MBA from Wharton Business School, University of Pennsylvania.

References
[1] Noia, B.; Goel, S.K.; Chakrabarty, K.; Marinissen, E.J.; Verbree, J., “Test-architecture optimization for TSV-based 3D stacked ICs”, 15th IEEE European Test Symposium (ETS), 2010, pp 24 – 29.

[2] Marinissen, E.J.; Verbree, J.; Konijnenburg, M., “A structured and scalable test access architecture for TSV-based 3D stacked ICs”, 28th VLSI Test Symposium (VTS), 2010, pp 269 – 274.

[3] Xiaoxia Wu; Yibo Chen; Chakrabarty, K.; Yuan Xie, “Test-access mechanism optimization for core-based three-dimensional SOCs”, IEEE International Conference on Computer Design, 2008, pp 212 – 218.

[4] Yibo Chen; Dimin Niu; Yuan Xie; Chakrabarty, K., “Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2010, pp 471 – 476.

[5] “Researchers Strive for Copper TSV Reliability” Semi Int, 12/03/2009- which has been removed from the web due to business conditions.

[6] Kitada et al. . “Stress and Diffusion Resistance of Low Temperature CVD Dielectrics for Multi-TSVs
on Bumpless Wafer-on-Wafer (WOW) Technology”, http://sogo.t.u-tokyo.ac.jp/ohba/news/AMC2010.pdf

[7] Zhiyuan He, Zebo Peng, Petru Eles, “Multi-Temperature Testing for Core-based System-on-Chip”, Design, Automation & Test in Europe Conference & Exhibition (DATE) Proceedings, 2010, pp 208 – 213.

[8] D.L. Lewis and H.-H.S. Lee, ‘‘A Scan-Island Based Design Enabling Pre-bond Testability in Die-Stacked Microprocessors’’, Proc. ITC 2007, pp. 1-8.

[9] Molavi, S.; Evans, A.; Clancy, R., “Protocol Aware Test Methodologies Using Today's ATE”, 17th Asian Test Symposium, 2008, p 273.

[10] Alexander Roskin A., Blank, D., “Protocol-aware ATE with Native Memory Emulation mode: enabling a paradigm shift for testing complex SoC devices”, submitted ITC 2011.

[11] Ken Smith, Peter Hanaway, Mike Jolley, Reed Gleason, Chris Fournier, and Eric Strid, “KGD Probing of TSVs at 40 um Array Pitch”, Proceedings ITC 2010, pp 1-10.

[12] Marinissen, E.J.; “Testing TSV-based three-dimensional stacked ICs”, Design, Automation & Test in Europe Conference & Exhibition (DATE) 2010 Proceedings, pp 1689 – 1694.

[13] Ang-Chih Hsieh; TingTing Hwang; Ming-Tung Chang; Min-Hsiu Tsai; Chih-Mou Tseng; Li, H.-C.; “TSV redundancy: Architecture and design issues in 3D IC”, Design, Automation & Test in Europe Conference & Exhibition (DATE) 2010 Proceedings, pp 166 – 171.

[14] Marinissen, E.J.; “Testing TSV-based three-dimensional stacked ICs”, Design, Automation & Test in Europe Conference & Exhibition (DATE) 2010 Proceedings, pp 1689 – 1694.

[15] JEDEC Announces Broad Spectrum of 3D-IC Standards Development, http://www.jedec.org/news/pressreleases/jedec-announces-broad-spectrum-3d-ic-standards-development

[16] Marchal, P. et.al.; “Verifying Thermal/Thermo-mechanical behavior of a 3D stack – Challenges and Solutions”, 2010 International Symposium on VLSI Design Automation and Test (VLSI-DAT), 2010, pp: 15 – 16.

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