A standard peripherals approach to adding flexibility to 32-bit MCU designsToday’s 32-bit microcontroller (MCU) designs integrate a wide variety of standard peripherals, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), universal synchronous/asynchronous transmitters (USARTs) and timers.
While this peripheral integration is intended to address a wide range of general-purpose applications, embedded developers commonly consider these on-chip peripherals to be “check box” items, and the implementation of this peripheral integration usually ends up providing limited value.
In addition, the lack of smart interconnectivity among peripherals often forces designers to add significant amounts of glue logic to ensure proper use of the MCU’s features, resulting in unnecessary incremental development costs and system complexity.
Standard MCU peripherals are intended to support a broad range of general-purpose embedded applications. However, peripherals often are integrated into 32-bit MCU designs with little or no thought about how they can enable a more cost-effective or simpler application implementation.
Let’s take a closer look at implementations of standard MCU peripherals that provide system-level value and application benefits that help designers get the most out of every feature in the MCU while simultaneously reducing the bill of materials (BOM) and simplifying the embedded design.
Innovative implementations of standard MCU peripherals, such as I/O with deterministic pulse generation and level shifters, USART input noise-filtering for reliable communications, capacitive-sense tamper detection systems, current-based communication using interconnecting digital-to-analog converters (IDACs) and synchronous current-to-voltage converter systems, can provide significant value for 32-bit embedded designs.
I/O with deterministic Pulse Generation and Level Shifters
Some 32-bit applications require the generation of one or more pulses with precisely-controlled pulse widths.
Examples include a trigger for an external event or a test pulse to stimulate an external device within a specific time window. A typical software-implemented I/O toggle cannot guarantee the pulse width since the software is subject to interruptions and latencies, and using a timer consumes a valuable and typically pin-constrained resource.
An innovative solution to this design challenge implements pulse generation at the I/O level (Figure 1 below). This system provides the capability to set the initial and final value of the I/O in one 32-bit register (allowing the initial and final value to be set in a single 32-bit word write) along with a mask register to enable multiple pins at any time and a programmable 5-bit delay time.
Click on image to enlarge.
Once initiated, the pulse generator waits for a number of peripheral clock cycles set by the delay time before driving the pre-programmed final value onto the I/O pin, enabling simple yet effective deterministic pulse generation. Figure 1 above shows a practical implementation of this feature at the register level.
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