Custom ASICs always offer the best performance, power consumption, security and unit cost of any silicon-based solution. Cell-based ASICs provide the best characteristics because the poly and diffusion layers for interconnect, and transistors can be sized to optimize speed, density, and power dissipation according to each particular cell's requirements.

This approach provides for a silicon-efficient design, but is expensive because it requires a full mask set. Mask costs increase sharply with shrinking process technology or feature size.

Indeed, the $250,000+ cost of a full 130 nm mask set and the lengthy design time associated with standard cell ASICs puts them out of reach for many products. In fact, in applications such as MP3 players or cell phones, the technology evolves so rapidly that the next generation product must be launched every six months -- about half the time required to implement a cell-based ASIC.

The pros and cons of gate arrays
Gate array technology uses an array of identical transistors with a metal interconnect to create logic functions. Since customization is accomplished through the routing, masks are required for only the metal interconnect and NRE charges are much are in the $100,000 to $150,000 range.

Design turn around is about three months " one-third the requirement for cell based ASICs -- because most of the silicon processing is done before" the die is "personalized". Since one set of under-layer silicon masks can serve more than one design, the engineering and mask costs associated with gate arrays tend to be substantially lower than those for cell-based ASICs.

Platform ASICS vs gate arrays
Platform ASICs have further improved the quick turn-around time and lower non-recurring eniginnering (NRE) cost of gate arrays by providing a pre-designed mix of metal programmable blocks and microprocessor cores, memories, analog blocks, or peripherals. With common IP blocks, such as a UART or serial interface, there is little value to be gained from building from scratch, so these pre-designed and validated cores are re-used, as is in a platform approach.

Many platforms can be defined using a standard product ARM-based design data base. In fact, many of these designs are prototyped using the standard product along side an FPGA for initial prototyping. Most systems have many elements in common, so a single platform based on an existing set of masks may be used for multiple ASIC designs. New masks are required only for the unique part of the design, which is implemented by adding a new metal interconnect with custom logic.

Structured ASIC features
With careful architectural design, structured ASICs can be designed with the right complement of fixed features to satisfy the requirements for a range of products in a given market or a family of evolving products for a particular customer. This intelligent re-use of pre-defined elements brings NRE charges down to an even lower level.

The time to market and technical risk are also reduced significantly with a platform ASIC because the wafer is fabricated by manufacturing only the metal interconnect layers. This process takes less than half the time required for a cell-based ASIC. Since the platform itself has already been verified, only the custom logic for the ASIC's "personality" need be.

Given this reduced design complexity, the development and prototype evaluation times can be substantially reduced with a structured ASIC, especially those using a common ARM-based architecture. Even so, gate arrays are less silicon efficient, resulting in substantially higher unit costs than cell-based ASICs. Gate arrays also tend to have worse speed and power characteristics.

For example, in a 180 nm process, a standard cell flip-flop consumes roughly half as much area as a D flip flop implemented in a gate array. Cell based ASICs have about twice the gate density and half the unit cost of a gate array implementation (See Figure 1, below).

Figure 1. D-type flip-flop in 180 nm gate array and 180 nm standard cell implementations.

Early structured ASICs once were expected to provide lower NREs than conventional ASICs and lower price points than high priced FPGAs. The fact is that FPGAs keep getting cheaper and structured ASICs' unit costs are rarely low enough to offset the relatively high NRE costs and risks. The re-programmability of FPGAs provides a measure of flexibility that can never be achieved by any ASIC.

FPGA/MCU Combinations
As a result, the majority of today's designs are implemented using an off-the-shelf standard product microcontroller and a low-cost, off-the-shelf FPGA. This MCU-plus-FPGA combination has effectively replaced ASICs in many applications.

A microcontroller with the right mix of peripherals implements the most of the application, while the FPGA is used for the "secret sauce" that differentiates the product, such as DSP algorithms or custom logic.

The re-programmability of both the MCU and the FPGA offer nearly perfect flexibility to meet changing market needs. There are no NREs and time-to-market is just about instantaneous.

FPGAs do have some drawbacks, however. The extra transistors required for programmability bloat FPGA die sizes to two or three times that of the non-programmable implementation. Routing and other constraints result in very low logic utilization in FPGAs. Only about 10% of the 150 gates in a typical FPGA cell will actually be used.

Thus, although FPGA unit costs do decline as volumes increase, prices stall at about 10,000 units. The next stop for cost-reducing a design is at 100,000 units, where unit volumes can support the NRE of conventional ASICs (Figure 2, below).

Figure 2. Unit Prices & Volumes for FPGAs, Standard Cell, Cell-based and MPCF ASICs.

Those extra transistors that enable FPGA programmability also gobble up power. FPGA cell sites are large requiring longer wire lengths and there are a lot of unused transistors within the cells consuming power.

Another less obvious reason is because they require a very uniform, structured clock tree with relatively few independent clocks, and they can not support significant amounts of clock gating to reduce current consumption. For example, a 65 nm Virtex 5 consumes over 3 Watts when executing a PCIe with 8 endpoints!

Security is another issue with SRAM-based FPGAs. Proprietary algorithms, that can take decades to perfect, are subject to piracy because the FPGA design resides in external memory.

Even if there is a security bit in the on-chip flash that prevents it from being read, the FPGA netlist must be re-loaded into the FPGA every time the system boots up, making it vulnerable to theft. Although some FPGAs have some security features, the IP is not nearly as secure as it is when implemented in silicon.