Incorporate power-saving methods at multiple levels in application-specific IP.

Increasing battery life without compromising performance and functionality is a prime concern for the handheld market. The form-factor and economics of this market also demand an ever increasing level of integration for these devices. Each generation of handheld devices sets more aggressive battery-life goals, making power reduction an important consideration for the system designer.

To achieve this objective, system architects must incorporate power-saving methods into all aspects of device implementation. Monitoring and analyzing patterns of application use reveals opportunities to optimize power. These opportunities should be recorded in a power-optimization specification that guides the selection of power-reduction techniques for each component in the system. Techniques to lower power can be applied to both software and hardware components.

A handheld device consists of a display unit, keyboard, and audio I/O, all of which are controlled by a system-on-chip (SoC) and associated peripheral chips. Power is supplied by a rechargeable battery. A typical SoC consists of two kinds of intellectual property (IP) blocks:

• Standard third-party IP blocks (for example, an embedded processor)

• Customer-specific IP (CS-IP)

This CS-IP is the "secret sauce" that differentiates the SoC in the product segment. The standard third-party IP blocks are designed by IP vendors using mature design methods. Because these blocks are intended for integration and reuse in multiple designs, power optimizations are built into their implementation. The extent of these optimizations also help differentiate an otherwise standard building block.

When your team hands off your SoC design to the ASIC designer, you challenge the ASIC designer to meet power-reduction targets by implementing multiple power-saving techniques to the CS-IP blocks. A combination of time-to-market pressure and functional integration requirements conspire to make the ASIC designer rely heavily on proven IP to implement an SoC for the handheld market. Product differentiation is achieved by integrating standard third-party IP with CS-IP to compete in an increasingly crowded and converged handheld device market. The proprietary CS-IP is designed by IP groups whose primary focus is on functionality rather than power.

Hence, an ASIC designer integrating a CS-IP block doesn't have the requisite knowledge of its micro-architecture nor details of its verification environment. Moreover, an ASIC designer working for an ASIC vendor that's integrating the SoC is often supplied the CS-IP as a hard-macro with an encrypted simulation model, further limiting the options to modify its implementation.

In spite of these challenges, an ASIC designer can use several techniques to reduce dynamic power consumption of CS-IP blocks in an SoC. Some of these techniques don't require extensive modifications to the CS-IP, which is particularly advantageous for those CS-IP that are supplied in a format that precludes synthesis or remapping of gates.

Clock gating
The clock distribution network consumes a major component of a typical SoC's dynamic power. Clock gating can be effective in reducing power, provided knowledge of the application and the CS-IP's switching activity is known. Clock gating can be done at multiple levels in the design--fine-grained (groups of flip-flops), medium-grained (sub-blocks of the IP), and course-grained (entire IP). The first two techniques require significant modifications to the CS-IP's internal logic (and aren't discussed here).

A complex CS-IP with multiple clocks will need a control-unit block in the SoC to implement coarse-grained clock gating. This control unit handles the sequence of events to disable and restore clocks. The power-delivery network to these clock buffers should be designed so that they can handle current surge when the clocks are restored. Special cells that minimize the additional delay caused by the clock gating logic should be used to implement this feature.

An extension of coarse-grained clock gating is to form a sequence of clock-gating events over multiple IP blocks. This technique is possible for a system architecture that includes a predictable data flow through multiple processing units. One example is a data-acquisition system that consists of a data-capture front-end, a processing engine, and a storage-unit interface. The on-chip control unit can sequence the clock gating across these functional units in response to a capture event.

The power savings from these techniques are proportional to the duration of time the clocks are disabled. Since the state information internal to the CS-IP is preserved when the clocks are disabled, this technique doesn't require modifications to the CS-IP blocks. The benefit from clock sequencing is only limited by the complexity of the control unit and sequencing of clocks to each functional unit.