Designing with an embedded soft-core processor
When designing an embedded solution, the designer will have product level requirements that mandate the processing of various inputs to yield predictable outputs.
There will be a number of acceptable options to choose from when selecting the type of design that will be used for the controller. The first solution is a “Discrete” microprocessor, which seem to be the most commonly used solution. The second solution is a “hard” processor core, which will be embedded in hardware as dedicated silicon in either an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).<>Alternatively, an embedded soft-core processor may be a viable solution where the processor is implemented in the primitives of an FPGA. The decision regarding the type of controller used is typically based on a balance between schedule, unit cost, space constraints, product lifetime, toolset, and flexibility needs.
Different options are available to a designer needing to select a microprocessor. Some options provide more benefits over others; however, not all options are a fit for every application. The key is to know what is needed for the application and then select the correct option that will suit the application. Three processing options will be briefly discussed here: the “discrete” OTS (Off the shelf) processor, a hard processor core, and finally the soft processor core.
A discrete OTS microprocessor solution is the traditional approach that designers have used. These types of processors are available from a multitude of vendors and have a wide range of features. A discrete microprocessor is implemented as an ASIC with a specific peripheral set along with the processor core.
Selecting a discrete processor that meets the application’s cost and functional requirements can be a time consuming process. There are times, however, where an OTS processor solution will not meet those requirements. An example would be an application that requires custom logic or a significant amount of peripheral functionality that is not available in a discrete solution.
In this case, the logical place to look is at a processor and peripheral set that can be tailored to the application and included with the custom logic that is needed for the application.
Hard Processor Core
A hard processor core has dedicated silicon on the FPGA. This allows it to operate with a core frequency and have a DMIPS rating similar to that of a discrete microprocessor. A benefit a hard-core provides is that it exists in an environment where the surrounding peripherals can be customized for the application.
Unfortunately, it does not provide the ability to adjust the core for the application, nor does it allow for the flexibility of adding a processor to an existing design or an additional processor for more processing capabilities. In addition, only specific FPGAs will have the option of having a hard-core; therefore, the choice of vendors and FPGAs are limited.
Soft Processor Core
A soft-core processor solution is one that is implemented entirely in the logic primitives of an FPGA. Because of this implementation, the processor will not operate at the speeds or have the performance of a hard-core or a discrete solution. In many embedded applications, the high performance achieved by the previous two processing options is not required, and performance can be traded for expanded functionality and flexibility.
Soft-core processors may be appropriate for a simple system, where the only functionalities are the manipulation of GPIO (General Purpose Input/Output). Moreover, they may also fit a complex system, where an operating system is incorporated and interfaces include Ethernet, PCI (Peripheral Component Interconnect), and DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), and any other custom IP.
Why Design with a Soft-Core
There are many reasons for selecting a soft-core processor over other processing options. The first reason is that this type of processor provides a substantial amount of flexibility through the configurable nature of the FPGA.
In an ideal product development process, all requirements are gathered and solidified before the design portion of a project ever begins. As much as engineers wish this were the case, this seldom happens. Requirements often change throughout the course of the design and, in the majority of cases, requirements are added. In addition, requirements are still being defined in a research and development situation.
Using a soft-core processor alleviates many of the issues encountered due to changing requirements, which can be detrimental to a project if using a discrete microprocessor solution. A soft-core processor solution will prevent the design team from being confined to a specific set of peripherals that may no longer fit the application as requirements change or new features are desired.
A soft-core processor allows a designer to add or subtract peripherals from the SoPC with ease. In many toolsets, adding and configuring a peripheral is typically done in a few short steps. Not only is the addition of a peripheral easy to do, but there are a wide variety of peripherals available from vendors.
The list of peripherals available includes memory controllers, timers, counters, GPIO blocks, UARTs (Universal Asynchronous Receiver Transmitter), and interconnects such as PCI, RapidIO, and HyperTransport. The list is constantly growing, giving a designer many options for constructing an SoPC. The peripherals and soft-core processor are designed in HDL (Hardware Description Language), enabling further customization of the system to be performed.
The method in which the peripherals are connected to the processor within the SoPC is flexible. The SoPC system is comprised of memory-mapped devices with read and write interfaces.
Each peripheral within a system has a similar read/write interface, creating a common interface to the processor and to other peripherals. The logic for the address decoding, arbitration, data bus sizing, and the connection of control and bus signals is encompassed within a set bus structure.
The benefit of a set bus structure is that it is handled and created by the toolset, leaving the designer to concentrate on creating the system peripherals. Situations will arise where a required OTS peripheral is not available. In this case, a custom peripheral can be created. Given that each peripheral has a similar read/write interface, a peripheral can be created without knowledge of what is or will be in the system. Having the ability to attach custom peripherals enables a designer to give a soft-core processor whatever functionality is required.
Using an SoPC enables a designer to construct a system that fits exactly what the requirements call for, avoiding cost and time spent configuring unnecessary features. Sometimes the microprocessor that has all of the features needed to meet the design requirements also contains more, unnecessary features.
For example, an application may call for a 32-bit processor, 256MB of SDRAM operating at 133MHz, and 2 10/100 Ethernet MACs (Media Access Control). In this scenario, the only discrete processor that is found also contains a PCI interface. Not only does this additional interface add to the cost of the part, but the interface also has to be taken into account when designing it into the product.
A soft-core processor in an SoPC eliminates the burden of doing a significant search for a discrete processor and having to handle undesirable, added functionality. The designer has the flexibility to create a custom system that contains only the functionality needed. Further, the system can be modified as needed to meet any future needs.
Customizable Processor Core
A soft-core processor also offers the flexibility of tailoring the core itself for the application. There are a few different levels of how this can be accomplished, depending on the vendor. On one level, things such as cache size can be easily adjusted.
Most toolsets offer the option to configure different cache sizes to suit what the application requires. A vendor may also offer different versions of the processor that have varying levels of performance. In this case, a higher performance version of the processor would have more pipeline stages, increasing throughput. This offers more flexibility to the user.
It is important to note that along with a performance increase there will also be an increase in the amount of logic elements that the processor will consume or the amount of memory that the processor will consume, leaving fewer resources for peripherals and custom logic.
On a higher level of complexity, a designer can take the source code for the processor core and modify it to meet the needs of the application. Being able to modify the source code to the actual processor core offers the greatest of flexibility that one can obtain. Not all vendors will offer source code for their soft-core processor solution; sometimes the core is encrypted.
Using an SoPC solution also offers flexibility external to the FPGA. A discrete microprocessor solution has a fixed pinout, sometimes making routing difficult. Since an SoPC exists in an FPGA, the pinout is flexible. This gives the board designer almost complete freedom with component placement, provided the FPGA still meets the timing constraints with the final pin placement.
Another benefit is that there are more GPIO available in an SoPC solution compared to a discrete microprocessor. The FPGA can be scaled up in size if necessary to accommodate any additional IO that is needed, whereas an ASIC solution restricts the IO use to what is on the IC; no expansion is available.
An SoPC solution also provides more options with prototyping possible solutions without a significant change to the hardware. This benefit in flexibility is mostly realizable when using hardware provided in the form of a development kit from the vendor.
Faster design cycles
Using a soft-core processing solution can reduce schedule in both the design and verification phases of a project. Constructing a system can be done in a short amount of time, since there are toolsets provided by vendors just for this purpose. Along with the OTS peripherals available, many of them come packaged with software drivers, which will help shorten the software development time.
Software can be tested earlier in the development cycle; no longer does a software engineer have to wait until the board design is complete, prototyped, and debugged. An SoPC enables verification of the software while verifying the hardware.
One option is hardware/software co-simulation. In the design phase of a project, the software and hardware are being developed in parallel. At some point, the two paths can merge and both the hardware and software can be simulated together to test functionality.
In an FPGA design, it is always part of the process to simulate the design before it is put in actual hardware. However, designing with an SoPC allows the project team to be able to verify the software running on the embedded processor along with the attached peripherals. The simulations are not restricted to only testing the embedded system; the entire FPGA can be simulated with software executing.
When hardware and software paths are ready to merge and system simulations are to be executed, the toolsets from the FPGA vendor do the majority of work preparing the design for simulation.
The tool will create the simulation project file, create a top level test bench, instantiate the processor and peripherals in HDL, and create generic, basic memory models if specified. The top level test bench that is generated can be expanded and modified enabling the designer to instantiate other modules, test other functionality, create stimulus, and monitor signals within the complete FPGA.
Along with generating necessary files to simulate the hardware, the development environment compiles C/C++ code into machine code. The machine code is included in a data file that is used to initialize the program memory. After these files are created, the complete SoPC can be simulated, with software running, testing for desired functionality.
FPGA vendors offer development boards as part of the development kit for a soft-core processing solution. These development boards can be used in addition to simulating the design. Utilizing the development boards in an SoPC design process enables the software and FPGA images to be tested on hardware before custom form factor boards are prototyped.
Traditional microprocessor vendors also have boards available for software development use. However, the soft-core processor’s development board allows the hardware designer to test out portions of the SoPC design on actual hardware, not just depending on simulations for confidence.
Testing the FPGA design with software on actual hardware earlier in the design process gives the design team more confidence and reduces the time spent debugging form factor hardware when it arrives. As flexible as the development platform is, the design team will not be able to completely test a design due to limitations with the hardware external to the FPGA.
Embedded logic analyzer. FPGA vendors offer the ability to embed logic analyzer functionality within the FPGA to monitor signals within the FPGA design. Having the ability to look at nodes deep within the hierarchy of an FPGA design provides great benefit when debugging and makes debugging easier and quicker. Beyond debugging purposes, the use of an embedded logic analyzer with a soft-core processor enables the design team to gain a deeper level of understanding and familiarity with the design, making future modifications easier and quicker task.
Migrating to a Soft-Core Processor
A situation may exist where an FPGA was designed without a soft-core processor, and it was decided later that having a soft-core processor would provide for a better solution for the application. Another situation may call for quick additions to the FPGA.
Adding a soft-core processor takes care of both of these situations in the timeframe required, as long as there are logic resources available in the FPGA. Designing the solution from the ground up in hardware is not feasible within a short timeframe. Having a configurable device with a processor implemented in logic allows for both of these situations to be addressed easily.
Multiple Processors. More complex embedded systems could benefit from the use of multiple processors to decrease the execution time by executing tasks in parallel. Soft-core processors and their accompanying toolsets can make the task of implementing multiple processor cores that interface with a common set of peripherals much more feasible and appealing to designers.
Also, there are not any additional BOM costs for adding a soft-core processor in an FPGA as long as there is enough space in the FPGA for the implementation. The only restriction on how many processors can be in an SoPC is the logic available in the FPGA. Therefore, when using an SoPC in a design where more parallel processing is required, adding another soft-core processor is a viable solution that does not impact hardware significantly.
For the most part, the soft-core design process is not too different from any other embedded development. Perhaps the only major differences are additional roles that may not be found in other development approaches and the stress on continuous communication between the different designer roles to maximize the use of additional features that may be available.
Don Arbinger is hardware design engineer and Jeremy Erdmann is embedded software design engineer at Plexus Technology Group.
This article is excerpted from a paper of the same name presented at the Embedded Systems Conference Silicon Valley 2006. Used with permission of the Embedded Systems Conference. For more information, please visit www.embedded.com/esc/sv.
1. Avalon Bus Specification Reference Manual, Altera, Revision 2.3
2. NIOSII Processor Reference Handbook, Altera, Revision 1.0, May 2004
Additional CMP Media/Embedded.com
1. Back to the Basics: All about FPGAs
2. Tackle team-based FPGA design
3. ASIC to FPGA migration: myth or reality?
4. Using softcore-based FPGAs to balance hardware/software needs in a multicore design
5. Optimizing DSP functions in advanced FPGA architectures
6. Maximizing DSP, embedded CPU performance in FPGA designs
7. Simplify your multiprocessor-based network design with multicore FPGAs