Techniques for Designing Energy-Aware MPSoCs " Part 1Power and energy consumption have become significant constraints in modern day microprocessor systems. Whereas energy-aware design is obviously crucial for battery-operated mobile and embedded systems, it is also important for desktop and server systems due to packaging and cooling requirements.
In such systems, power consumption has grown from a few watts per chip to over 100 watts. As desktop/server (and even embedded) systems evolve from the uniprocessor space to the multiprocessor system-on-chips (MPSoCs) space, energy-aware design will take on new dimensions.
Techniques for energy and power consumption reduction have been successfully applied at all levels of the design space in uniprocessor systems: circuit, logic gate, functional unit, processor, system software, and application software levels.
The primary focus has been on reducing active (dynamic) power. As technology continues to scale up accompanied by reductions in the supply and threshold voltages, the percentage of the power budget due to standby (leakage) energy has driven the development of additional techniques for reducing standby energy as well [9,10].
|Figure 2.1. Components of power consumption. Is-c, short-circuit current; Ioff, leakage current; Idyn, dynamic switching power.|
Figure 2-1 above illustrates the components of power consumption in a simple CMOS circuit. In well-designed circuits, Is-c is a fixed percentage (less than 10%) of Ion. Thus, active power consumption is usually estimated as:
Pact = Cavg V2dd (Act) fclock
where Cavg is average capacitive load of a transistor, Vdd is the power supply, fclock is the operating frequency, and Act is the activity factor that accounts for the number of devices that are actually switching (drawing current from the power supply) at a given time.
This definition of active power consumption illustrates the significant benefit of supply voltage scaling—a quadratic reduction in active power consumption. However, it is important for high performance that VDD + 3VT so that there is sufficient current drive.
Thus, as supply voltages scale, threshold voltages must also scale, causing leakage power to increase. As an example, the leakage current increases from 20 pico Amperes per micrometer when using a Taiwan Semiconductor Manufacturing Corporation (TSMC) CL018G process with a threshold voltage of 0.42V 0.25V. Standby power consumption due to subthreshold leakage current is estimated as:
where Iof f is the current that flows between the supply rails in the absence of switching and KL is a factor that accounts for the distribution/sizing of P and N devices, the stacking effect, the idleness of the device, and the design style used.
In a CMOS-based style, at most half of the transistors are actually leaking whereas the remaining are ON (in the resistive region). As oxide thicknesses decrease, gate tunneling leakage will also become a significant source of standby power. This component of standby power is not included in the above equation and is not a target of the techniques presented in this chapter.
This series of articles surveys a number of energy-aware design techniques for controlling both active and standby power consumption that are applicable to the MPSoC design space and points to emerging areas that will need special attention in the future. Our model MPSoC system is depicted in Figure 2-2 below.
|Figure 2-2. Model MPSoC. I$, instruction cache; D$, data cache|
Energy-aware processor design
Many techniques for controlling both active and standby power consumption have been developed for processor cores . Almost all of these will transition to the MPSoC design space, with some of them taking on additional importance and expanded design dimensions. Figure 2-3 below shows the processor power design space for both active and standby power .
|Figure 2-3. Processor power design space. DFS, dynamic frequency scaling; DVS, dynamic voltage scaling; DTM, dynamic thermal management.|
The second column lists techniques that are applied at design time and thus are part of the circuit fabric. The last two columns list techniques that are applied at run time, the middle column for those cases when the component is idle, and the last column when the component is in active use. (Run time techniques can additionally be partitioned into those that reduce leakage current while retaining state and those that are state-destroying.)
The underlying circuit fabric must provide the "knobs'' for controlling the run time mechanisms - by either the hardware (e.g., in the case of clock gating) or the system software (e.g., in the case of dynamic voltage scaling [DVS]).
In the case of software control, the cost of transitioning from one state to another (in terms of both energy and time) and the relative energy savings need to be provided to the software for decision making.