Techniques for Designing Energy-Aware MPSoCs: Part 3Computation and storage energy directly benefit from device scaling (smaller gates, smaller memory cells), but unfortunately the energy for global communication does not scale down.
Projections assuming aggressive physical and circuit level optimizations for global wires  show that global communication on chip will require increasingly higher energy, the majority of it being active energy.
Hence, communication-related energy is a significant concern in future MPSoC systems that will create many new challenges that have not been addressed in traditional high-performance on-chip interconnect design.
In this section we will explore various communication energy minimization approaches, moving from simple architectures (shared busses and point-to-point links), to complex advanced interconnects (networks on-chip [NoCs]) that are applicable to MPSoCs.
The simplest on-chip communication channel is a bundle of wires, often called a bus. To be more precise, however, a bus can be significantly more complex than a bundle of wires. On-chip busses are highly shared communication infrastructures, with complex logic blocks for arbitration and interfacing. In an effort to maintain consistency with the surveyed literature, in the following we will use the term ''bus'' just as a synonym for a set of bundled wires.
It is, however, important to remember that implementing encoding schemes in real-life designs requires maintaining compliance with complex SoC bus protocols. This is not an easy task, as outlined in Osborne et al. .
Bus Encoding for Low Power
Bus data communication has traditionally adopted straightforward encodings and modulation. The transfer function of the encoder and modulator of binary non-return-to-zero input streams was implicitly assumed to be unitary. In other words, no modulation and encoding were applied to the binary data before sending it on the bus. Low-energy communication techniques remove this implicit assumption, by introducing the concept of signal coding for low power.
The basic idea behind these approaches is to encode data sent through the communication channel to minimize its average switching activity, which is proportional to dynamic power consumption in CMOS technology. Ramprasad et al.  studied the data encoding for minimum switching activity problem and obtained upper and lower bounds on transition activity reduction for any encoding algorithm.
This important theoretical result can be summarized as follows: the savings obtainable by encoding depend on the entropy rate1 of the data source and on the amount of redundancy in the code. The higher the entropy rate, the lower the energy savings that can be obtained by encoding with a given code redundancy.
Even though the work by Ramprasad et al.  provides a theoretical framework for analyzing encoding algorithms, it does not provide general techniques for obtaining effective encoders and decoders. The complexity and energy cost of encoding and decoding circuits must be taken into account when evaluating any bus-encoding scheme.
Several authors have proposed low-transition activity encoding and decoding schemes. To illustrate the characteristics of these schemes in a simple setting, we consider a point-to-point, one-directional bus connecting two modules (e.g., a processor and its memory), as shown in Figure 2-10 below.
|Figure 2-10. Bus encoding: one-directional communication.|
Data from the source module are encoded, transmitted on the bus, and decoded at the destination. A practical instance of this configuration is the address bus for the processor/memory system. If the bus has very large parasitic capacitance, the energy dissipated in driving the lines during signal transitions dominates the total energy cost of communication (including the cost of encoding and decoding). However, as discussed in the following, this assumption has to be carefully validated whenever a new encoding scheme is proposed.