Beefing up the Cortex-M3-based MCU to Handle 480 Mbps High-speed USBThe universal serial bus (USB) has completely replaced UART, PS2, and IEEE-1284 parallel interfaces on PCs, and now is gaining wide acceptance in embedded applications. Most of the I/O devices (keyboards, scanners, mice) used with embedded systems are USB-based for good reason.
Since the USB is a well-defined standard that is guaranteed by the USB consortium, any USB-certified device from any vendor will work in a plug-and-play fashion with any USB-certified device from any other vendor.
Multiple devices can operate on the same bus without affecting each other at all. It is not at all surprising that the majority of 32-bit flash MCU and MPU vendors offer some form of USB interface as a standard peripheral: USB host, USB device, USB OTG " usually limited to the "full-speed" specification of 12 Mbps (Figure 1, below).
|Figure 1. USB Block Diagram|
Now, the USB standard is set to solve another issue for embedded systems: the exponential growth in data rates. Five years ago, a data rate of 10 Mbps was considered high. A 12 Mbps full-speed USB, 10 Mbps SPI or 400 kps I2C interface could cover the data requirements of nearly any embedded application.
Today, however, with the advent of ever increasing sizes of log files and the growing sophistication of user interfaces, data rates of even tens of Mbps are not high enough to provide an adequate user experience. Log files of Gbytes must be transferred between systems in 10s of seconds and information collected from different PCBs within a system transferred to a graphical display unit.
Enter "high-speed" USB. With a bandwidth of 480 Mbps high-speed USB can meet today's demand for tens of Mbps and tomorrows demand for hundred of Mbps. It provides a well-understood, easy-to-use vehicle to handle large amounts of data and interconnection both between systems and between the printed circuit boards (PCBs) inside a system.
It will undoubtedly soon be adopted for inter-chip communication on a single PCB, bypassing the physical layer and removing the need for cable connections. Systems supporting this technology are forecasted to ramp in 2009.
Clearly microcontrollers will have to add USB HS support to keep up with the market. But the question is: How do you build a microcontroller that can handle the data load from a 480 Mbps USB interface, while meeting the power consumption and real-time constraints of an embedded system.
Sustaining a 480 Mbp data rate in a 400MHz ARM9-based microprocessor with an on-chip cache memory connected to a single plane high-speed external memory is pretty easy. Running it on a 100 MHz Cortex M3 flash MCU, executing from relatively slow flash memory is a whole other story.
Can the Cortex-M3 handle all these data transfers while running process-intensive tasks such as data processing algorithms, file systems and communication protocols?
The solution to this problem is to adapt the multi-layer bus architecture (Figure 2 below) used in ARM9 microprocessors to the Cortex M3 and divide the memory space into multiple blocks distributed within the architecture to secure real-time critical processing when high-speed data is transferred via DMA in parallel.
|Figure 2. High-data-rate-architecture.|
Direct memory access (DMA) is critical. Using the CPU for transfers would overload the CPU, likely preventing it from processing the application and real-time control tasks. Ideally, three types of DMAs must be connected to all low- and high-speed peripherals to minimize the data transfer load on the bus and memories, and to free the processor for the data processing and system control tasks.
DMAs with built-in buffers for improved tolerance to bus latency and burst transfer and linked list support are relatively bulky and reserved only for the highest speed interfaces.
They offer a high level of CPU independency and minimum bus usage. Due to the higher cost per channel, global usage of these full featured DMAs on each on-chip peripheral is not feasible.