PROJECT: You don't need a fab to build your own CPU!
As you can see from figure 1, the system is made up of the MIC 1 CPU, an eight bit rom memory used to store the program, a 32 bit rom used to store the constants of the 'constant pool' area, a 32 bit ram, a full duplex uart (I haven’t used FIFO buffers on the tx line modifying instead the OUT instruction with the insertion of a micro programmed delay in it), and some glue logic used to implement the decode of the addressed component by the CPU.
Fig 1: Here’s the overall picture of our embedded system. Thanks to FPGA’s technology, you can look at the Spartan 3 device as a big box of bricks with which you can play around.
To see a bigger version of this graphic click here.
Given the synthesized version of the CPU can run at a frequency slower than the one given by the quartz oscillator present on the board, I’ve had to use a frequency divider (the DCIM component) in order to get a clean and scaled down version of the original clock signal.
Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs(reference 2) explains how you can raise or lower the clock frequency and do many other things without adding an external oscillator on the dip socket provided on the board.
The only external resource used, is a simple RS232 cable and a pc running a terminal program, as you can see by figure 1. As on modern machines there’s the lack of such a gadget, I’ve resorted to an USB serial dongle plugged directly in the serial connector of the board.
Fig 2: The board offers a lot of peripherals. There’s even a VGA plug. I’ve used only a serial connector in my project, so the whole system can be hosted on a cheaper and simpler board.
As you can understand from the VHDL code posted on the FTP site, describing the system (the 'sistema_mic1.vhd file ), once you have developed the components, it is a very simple to assemble the embedded system. Thanks to the board’s design and the low usage of FPGA resources, this project can be used as the starting point for more challenging embedded systems.