Validate hardware/software for nextgen mobile/consumer apps using software-on-chip system development tools
A new breed of mobile smartphone platforms and sophisticated embedded consumer devices is now emerging requiring applications software and extensions that go far beyond just enabling user-level software customization.
The delivered “system” is no longer tied to any single or particular set of applications, but rather makes use of system software /hardware combinations that can adapt and evolve dynamically along with the needs of the user.
Enabling this new generation of electronic systems now requires system and system-on-chip (SoC) vendors to deliver complete software stacks along with their products (i.e., firmware, diagnostics, drivers, real-time operating system (RTOS), and middleware). Whereas in the past the system company was viewed as the “customer” by the semiconductor company, in this new world, both companies will behave more like channel partners, collaborating to deliver “application-ready” platforms/systems to the end user.
In this new paradigm, the next generation of SoC becomes much more sophisticated. Some in the industry have coined new terms, such as “solution SoC” (SSoC) or software on chip (SOoC), to highlight the fact that such products are trying to do more than support just one or a few “converging” applications (e.g., voice + music + video).
To give a consumer market example, the SSoC is focused on addressing the end user’s lifestyle, i.e., providing a universal platform on which any number or variety of software applications can operate. These trends began to emerge nearly 10 years ago with the Texas Instruments OMAP platform and NXP (Nexperia), and they accelerated with the arrival of the iPhone, Android, and other platforms.
As a result, the costs associated with software development and hardware-software integration/verification have become the largest and fastest growing portion of total SoC/SSoC design costs (Figure 1 below).
Figure 1: Breakdown of average total IC design costs for different design activities at different technology nodes
Enabling hardware/software stack development
Integrating and delivering complete software stacks with working silicon is a big stretch for today’s semiconductor/SoC and system companies, especially because meeting time-to-market requirements implies the need for application-driven hardware/software development (i.e., where system requirements and specifications are driven by the targeted range of software applications).
Addressing this challenge requires an integrated hardware/software (HW/SW) development environment that can comprehend the entire system HW/SW development space, starting from application SW and the algorithm-level of HW abstraction all the way down to lower levels of the SW stack (e.g., drivers and diagnostics) and register-transfer-level (RTL) HW.
Such an environment must not only encompass SW development and debug, but co-validation and co-verification as well. The engineering tasks and current challenges associated with developing the next generation of systems/SoCs can be categorized broadly into five areas:
High-level SW development (applications development): products today are all about the applications. As such, we are seeing a new approach to system design in which companies begin projects with an understanding of the needs of the applications that will run on the end system. Then, they use that understanding to develop an optimized platform to support the applications.
Even with this new approach—where the OS is free, comes with an SDK, is based on open source (Android, Linux, etc.), and is being designed to be HW independent—individual companies would like to differentiate based on the connection to and optimization of the underlying drivers and HW.
Although on the surface, , the application developers (especially in Android-based systems) are more isolated from the HW and even from the SW drivers; during the system bring-up process, they need to wait for many layers of the SW and HW to be brought in before they can run and test their applications on top of the “real” HW. This delay can create different surprises (power, performance, functionality) very late in the design process.
Mid-level SW development (OS and middleware porting/integration): the demands in this area represent one of the biggest challenges for SoC/system vendors going forward, and will require significant adaptation of their current development processes. As little as two or three years ago, this effort was done almost exclusively post-silicon (by the OEM vendor, rather than the SoC vendor). Nowadays, market pressures are forcing SoC and system companies to take responsibility for mid-level SW development and integration, early in the design phase.
Many of us have seen the blue screen as we try to boot the operating system in a new product for the first time. To reduce risk and compress development schedules, SoC and system companies want to complete as much of this development pre-silicon (using a combination of virtual prototyping and HW-based verification technologies) and need to be able to link their post-silicon environment to pre-silicon platforms during the debug process.
Unlike high-level SW development, in this scenario, HW and SW must be debugged concurrently. The current lack of integration between flows for SW development, virtual prototyping, RTL simulation, and acceleration/emulation has created significant barriers to engineering productivity Time-To-Market and, ultimately, company profitability.
Low-level SW development (drivers, diagnostics): because of the increasing complexity of HW IP over the past few years, development of low-level SW and HW IP has gone hand-in-hand. The complexity and sophistication of drivers, diagnostics, and other related SW has grown together with that of the HW components they support.
One of the greatest challenges has been to create flows and methodologies to enable parallel design, debug, and verification of HW-dependent SW together with HW, within a unified, multi-level simulation and HW-assisted verification environment.
TLM-driven design and verification: in any new design, typically 80-90% of the blocks are reused from previous designs or sourced from third parties. However, the remaining blocks (and how they are combined to form the overall SoC/system architecture) provide the vital differentiation that is a key to market leadership.
Now that the amount of effort and investment being channeled into system SW development typically exceeds that of system HW, the ability to automatically retarget the HW, its verification environment, and verification IP to accommodate SW requirements—and to still increase the overall productivity of HW design—are more critical than ever.
RTL-driven development flows are more than 20 years old and were optimized for “HW-first” SoC development. Under this old paradigm, HW was usually considered “fixed” and engineering teams would typically adapt the SW to meet the constraints and limitations of the HW. In today’s SW/application-driven world, the situation is reversed.
Because the majority of the system complexity, value, and cost of development are in the SW, changes to the SW and overall HW/SW verification are often more difficult and costly than HW changes. Therefore, in the “new world order” of system HW adapting to system SW requirements, the ability to validate HW architectures in a SW-context and to rapidly retarget HW to accommodate SW changes becomes more critical.
Transaction-level modeling (TLM)-driven hardware IP development addresses this need. It enables design teams to start HW design at a higher level of abstraction, where it can interact directly at a functional and transaction level with SW prior to any architecture decisions, and then automatically be architected and implemented to meet whatever performance requirements (latency, throughput, size, power) are dictated by the application and system SW.
The ability to automatically retarget/implement HW to any ASIC or FPGA technology also enables rapid transition between simulation/prototyping environments; for example, from TLM/RTL running in SW simulation to RTL running in a HW-assisted verification platform.
System/SoC integration, verification, and validation: Historically, the requirements for this stage have been addressed with simulation, simulation acceleration, logic emulation, or FPGA-based prototyping. In most cases, the level of reusability and automation to migrate from one environment to another among these solutions was poor.
Also, while very useful for low-level SW development, these approaches have major limitations when used for mid-level and application-level SW development. A major desire for SoC developers has been the ability to integrate these systems together with virtual platforms within a unified test/verification environment. For a variety of reasons, this has remained an elusive goal.
To address these five development tasks successfully and reduce overall system integration time, multiple integrated solutions that leverage a variety of technologies to address the challenges of parallel HW/SW development are required.
Solution stack features and capabilities.
The key elements of this new solution stack (Figure 2, below) fall mainly into three areas: Acceleration/Emulation, FPGA-based prototyping, and virtual prototyping. Each one addresses a different layer of the SW stack and is being used in a different phase of the design.
Acceleration/Emulation provides excellent scalable capacity and debugs capabilities and is best used for full SoC/System validation.
FPGA-based prototyping serves well as the post-RTL SW development platform (emulating a sub-system for large complex designs). RTL simulation is being used mostly for IP, sub-system, and portion of the SoC integration. It could be extended to low-level SW and registers tests and potentially as a stretch goal toward firmware and diagnostics verification.
Virtual prototyping provides excellent flexibility and serves as a SW development platform primary at the pre-RTL phase and can also easily get distributed to many developers.
Figure 2: Application-driven hardware/software integration elements
The electronics and semiconductor industries have undergone a major shift in the past decade, where software has eclipsed hardware as the main driver of system development cost, schedule, and risk.
These advances promise to add automation and increase both the productivity and capability of engineers to perform the following tasks:
System architecture exploration, by enabling engineers to build executable specifications and analyze architectural performance and tradeoffs before any system HW or SW components have been developed.
Reusable design and verification IP development, by providing automated synthesis to RTL from a high level of abstraction, as well as automated management of the verification process.
Embedded SW development, by enabling engineers to commence SW development on top of “virtualized” HW platform as early as fundamentally possible.
HW/SW validation and verification, by enabling HW/SW integration to start earlier (at the pure functional level), to progress smoothly as system implementation details are added, and to automatically verify HW/SW interoperability in parallel. Availability of HW/SW platforms with advanced methodologies is essential for a successful process here.
Arming HW and SW engineers with these new capabilities will enable them to meet the challenges of developing the next generation of electronic systems, dominated by software.
Ran Avinun is Product Marketing Group Director for systems design and verification at Cadence Design Systems.. With 11 years in senior marketing management positions at the company with focus on HW-assisted verification and the ESL market segments, he has 23 years of experience in the EDA and the semiconductor industries. Previously Avinun was at Quickturn, the inventor of In-Circuit Emulation (that was acquired later on by Cadence), Chip Express (a fast ASIC prototype manufacturer) in engineering and marketing roles. He began his career as an application engineer with Daisy Systems. Avinun holds a B.S.E and M.S.E in electrical engineering from the Technion and Tel-Aviv University in Israel and an MBA from the University of Phoenix in California.