The key to realizing full multicore design functionality
Advancing Moore’s Law
The move to more advanced process nodes has been a key driver in keeping up with Moore’s Law. The migration to the 40 nanometer (nm) process provided an impressive performance boost and the move to 28 nm will do the same, but today’s applications require more.
Today, the largest benefit derived from a new process node is the possibility of integrating more of an application’s functions into a single device. Hence it is a key enabler for SoCs. The first and most obvious tactic to leverage the integration potential for boosting performance is by adding programmable cores.
Multicore devices are characterized as either homogeneous, meaning all the processing cores are the same or heterogeneous, where there is a mix of core types. In fact, nearly all applications require a mix of processing capabilities including signal processing and control code. DSP cores and ARM RISC cores are ideal for this processing mix.
At Texas Instruments, the latest DSP cores support both fixed-and floating-point operations and perform VSP at high clock rates, simplifying algorithm development and deployment. Various ARM cores are available, allowing the SoC provider to optimize the RISC core selection to match processing requirements, power dissipation and process node.
From an architectural perspective, it is important to support homogeneous core implementations. Homogeneous devices (all ARM or all DSP) can be created from a heterogeneous architecture but the reverse is rarely true without severe performance degradation. Figure 1 below illustrates the KeyStone multicore architecture that TI engineers developed, an example of a heterogeneous multicore architecture.
Figure 1. TI’s KeyStone multicore architecture
Multicore Navigator
The architecture is made up of functional elements packaged in a way to facilitate application flexibility and scalability.
A flexible architecture is designed with the ability to easily add or remove elements as an application dictates. Applications such as wireless base stations and radar array processing have very similar processing and I/O requirement but quite different acceleration and coprocessing requirements.
Layer 1 PHY accelerators are mandatory for wireless base stations but are not needed for radar array processing. While it is unlikely that the same organization is developing both radar and base station products, they still benefit from the cost savings and volume benefits that accrue to the SoC developer.
When there are a range of products, scalability in the SoC architecture is very important to add or remove processing elements to address varying requirements. Today, wireless base stations range from small cell femto products to large scale multicell macro base stations. Similarly a radar manufacturer may have needs for small and large scale devices.
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