Dealing with multi-Vt & multi-voltage domain timing/temperature inversion challenges
The results we have shown are not in line with the normal assumptions made about temperature inversion effects. Why this is so may have to do with the fact that the temperature, input transition and output capacitance are not the only factors that govern the delay characteristics of a cell.
The variation in cell delay with temperature depends on the circuit voltage as well. In this case, when the voltage of the circuit is reduced to 0.9V, the trend line (as shown in Figure 5 below) followed the temperature inversion effect perfectly showing higher delays at cold temperatures.
Figure 5. Delay Characteristics of chain of inverter at 0.90 V(To view larger image, click here).
Based upon above mentioned experiments, it is fair to conclude that for 0.90V (i.e. for low voltages), the worst setup timing corner is the worst-cold and for 1.1V (i.e. for comparatively higher voltages), worst setup timing corner is the worst-hot.
However things became more exciting and complex when the same analysis was carried out on cells with different Vt values across various voltage levels. We generated Vt variants of library values by changing the doping concentration. These are High-Vt, Std-Vt and Low-Vt. Also the SoC is partitioned in different voltage domains.
To capture the whole picture as in the real design scenarios, analysis was done on all the cell variants at different voltage levels (0.9V, 1.0V and 1.1V)
These results (Figure 6 below) showed that High-Vt cells shows more pronounced temperature inversion effect at lower voltages (0.9V) but at higher voltages the hot temperature still act as worst corners. Std-Vt cells are similar to High-Vt though the impact in delay due to the temperature inversion is moderate. Low-Vt cells are almost immune to temperature inversion effect from the voltage range of 0.9V to 1.1V.
Figure 6. Delay Characteristics of chain of inverter at 0.90, 1.0V, 1.1V with Vt variation. (To view larger image, click here.)
This ambiguous behavior at different voltages with multi-doping taken into account is caused by a race condition between the mobility and threshold voltage (Vt) effects on the cell to dominate the delay.
From results described elsewhere in the technical journals, it is clear that the cell delay is inversely proportional to the mobility and directly proportional to the threshold voltage (Vt). Also, mobility and threshold voltage (Vt) both decreases with increase in temperature. So, as the temperature increases, the delay of the cell can
* Decrease due to decrease in threshold voltage (Vt).
* Increase due to decrease in the mobility.
Therefore, because the delay of a cell may decrease or increase depending on the dominant effect of mobility and threshold voltage (Vt), that is what defines the resulting thermal trend related to temperature inversion effects.
As seen in the results, at 1.1V (the gate overdrive voltage) is large enough so that the decrease in threshold voltage due to temperature variation is negligible. But the mobility effect dominates, with the result that the delay of the gate increases with temperature increases.
But at 0.9V the gate overdrive voltage (Vdd ? Vt) has reduced such that the decrease in threshold voltage effect dominates and delay decreases with the increases in temperature.
So, at 40nm and below, the threshold voltage (Vt) has not been reduced much but the supply voltages has reduced considerably to cater low leakage power concerns. The result is that the gate overdrive voltage (Vdd - Vt) has reduced and thus more prominent temperature inversion effects are observed.
That is why in our analysis, shown in Figure 4 (1.1V), the delay trend of the inverter did not follow the temperature inversion as compared to the situation in Figure 5 (0.9V). There the overdrive drive voltage was lower (due to lowering of circuit operating voltage), and as a result, the delay trend of the inverter varied inversely with temperature.
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