Reducing signoff corners to achieve faster 40 nm SOC design closure
Variations and their effects
Process, voltage and temperature are individually responsible for making the silicon gates act differently. A particular process value which determines the gate silicon is doped properly (a good process) is needed to provide best delays. With high voltages, gates get charged or discharged quickly, providing faster delay.
As temperature decreases, majority charge carriers collide less often, making the silicon gates respond more quickly, resulting in lower delays. On smaller technology nodes, after a threshold is reached, the Temperature Inversion Effect can introduces the reverse effect, with the result that gate delays can vary in opposite direction to temperature effects.
At higher geometry process nodes, such as 250nm, 130nm it was enough to consider two corners - worst & best - where the effect of temperature inversion was not prominent. But at C90 geometries and smaller the silicon quality may demand two more corners, such as best-hot & worst-cold.
Summarizing the above and converting this into an SOC spec we can now introduce the following four corners to define the silicon variation. (For example, an SOC voltage range of 1.08V - 1.32V and a temperature range of -40C to 150C). This is shown below in Table 1.
Table 1: Corner definition with PVTs
Interconnect variation
Each metal interconnect wire - depending on its dimensions - contributes its resistance and capacitance values to such things as delay. The interconnect delay of a net, which is the combination of several metal wires and VIA connections, are modeled in the form of RC networks.
For the 90nm and higher process technologies, the interconnect delays doesn’t contribute much towards the timing path delay nor did the variation of net delays. Even C-Max (C max & R min) and C-Min (C min & R max) corners were enough to cover all silicon variation.
But as the technology shrinks toward smaller nanometer regimes, interconnect delay becomes more dominant compared to gate delay. At this point, calculating interconnect delay is more crucial and plays a major role in achieving an accurate timing check. The result: two more RC corners must be introduced - Delay Corner (R x C maximum, Cc minimum) and Crosstalk corner (R x C minimum, Cc is maximum). Temperature also becomes a key factor in interconnect variation.
Timing Signoff Corners
Combining silicon variation and interconnect variation we have following 16 applicable corners for timing signoff, as shown in Table 2, below.
Table 2: Sixteen (16) signoff corners
Usually for setup timing checks, it is quite easy to determine the signoff corners. But at each process shrink, hold checks are critical in every corner because of a direct linear dependency on clock skew. As a result, to make an SOC work for all PVT values, it is necessary to check “holds” on every defined corner.
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