Embedded 3D graphics is here, but 2D is still important: Here’s why
Here is a brief description of the individual blocks in the Iris pixel engine and how they combine the best of the raster and vector-graphics techniques.
1. Pixel Engine. As Figure 4 below shows, this block is the heart of the Iris engine. This flexible pixel-processing unit can have two instantiations of pixel pipelines, one for blit and the other for display.
The engine, which can be configured through an AHB interface, offers interrupt signals. Its main sub-units are its fetch, store, and core pixel-processing units. Their functions, in respective order, are to fetch pixel data from memory, store, and process them as needed. The pixel-processing units will be discussed in more detail next.
2. Fetch Unit. This is a key part of the pixel engine. As the name indicates, the fetch unit gets pixel data from ROM or RAM storage units at high speed. It allows an image size as high as 1024x1024.
Click on image to enlarge.
Figure 4: Iris Block Diagram
There are three different types of this unit, depending on the action it performs on the graphics data while fetching:
* ROT: Rotates the incoming bitmap
* RLD: Decompresses the run length encoded bitmap
* Light: Alpha blends the incoming pixel data
The fetch unit will start working after it receives a kick signal from the display side. It also performs color conversion on the graphics data.
Optionally, it can also perform bilinear filtering, which is useful when the image is being rotated. Right before the graphics data is sent out of this block, the unit performs multiplications with constant color/alpha or an alpha pre-multiplication.
3. CLUT. The Color LookUp Table can be used to either look up or index colors. In the first role, the table can be used to neutralize non-linearity of color transmission or adapt the individual characteristics of the display panel.
In the second role, the table contains reduced-length color code that points to the raw color values. This can help reduce memory consumption.
The block consists of a RAM with 256 entries. Each entry is 10-bits wide for each color component. CLUT is fully software programmable. 4. Matrix. This unit performs linear color correction or conversion (e.g., YUV to RGB conversion). The unit allows for full programming of the matrix and offset coefficients and supports 3x3 matrix size. The unit can operate in one of the following three modes:
* Neutral mode: The unit does not perform any operation on the incoming data.
* Matrix mode: The incoming pixel data goes through a matrix conversion, as discussed previously.
* Pre-multiplication mode: The incoming pixel value (RGB) is pre-multiplied with the incoming alpha value.
5. Scalar. As mentioned earlier, a key functionality of Iris is the ability to upscale or downscale bitmaps through the scalar unit. This brings it closer to vector graphics engines. The unit is comprised of two components:
* for horizontal scaling
* for vertical scaling
The scalar can handle bitmap sizes from 1x1 up to 1024x1024. It also supports point and bilinear filtering to allow fine image quality.
6. ROP. The ROP unit performs the standard raster operations (e.g., AND, OR, NOR) on pixel values. This unit can take up to three input channels of pixel data.
7. BitBlend. This unit performs various blending operations on two input pixel sources. It performs both OpenVG 1.0 and OpenGL 2.0 blending modes.
8. LayerBlend. This unit is used to blend or merge two video layers. It can either perform an alpha-blending operation between the two layers or can just operate in a transparency mode with one layer getting higher priority over the other.
9. Store. This unit stores pixel data received from the pixel engine into memory. Image sizes up to 1024x1024 are supported.
10. ExtDst. This is an output interface of the pixel engine for the pixel stream. It is used to pipe the stream to the display controller so that the content can be shown on the LCD screen.
11. Display Controller. This unit generates the required control signals for operating a display in RGB mode using HSYNC and VSYNC signals as timing references. The pixel data from the pixel engine is transmitted to the display controller through a FIFO interface. The unit supports display clocks up to 40MHz.
The display controller has a dithering unit that can help smooth the appearance of image data on a low-resolution display panel. Both spatial and temporal dithering modes are supported.
12. Timing Controller. This unit, usually referred to as TCON, generates control and data signals to directly communicate with the column and row drivers of a display panel. The freely programmable waveform of the generated timing control signals allows emulating almost every timing controller IC. The unit supports both single-ended TTL and differential RSDS signaling modes.
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