Designing embedded SoCs using older resistive technologies

Mayank Verma and Vijay Bhargava, Freescale Semiconductor

May 30, 2012

Mayank Verma and Vijay Bhargava, Freescale Semiconductor

Coming up with a solution
To find a better method for routing, we performed a series of experiments where we tried to improve upon the timing. The first thing we thought of - the usual Post-Route Optimization and buffer addition techniques - didn’t help much since Router by itself was not able to improve the net topology much. As a result the RC parasitic for most of the critical nets remained the same and maintained the timing status-quo. Other things we tried, like buffer addition in the critical path, only worsened the timing scenario since they added to the parasitic of already overloaded nets.

Finally we zeroed-in on a multi-step approach, presented below, which helped us improve the timing and enabled the timing closure:

1. Taking post-routed RC parasitic back to postCTS optimization: As noted earlier, because the consistency of net delays from the tools is heavily dependent on the accuracy of parasitic extractions performed during clock tree synthesis, we first went back to the post CTS stage (with all routing removed) and made sure that it uses the actual measured RC values from the post-routed stage. Optimizing the CTS results in this way allowed us to improve the timing results by about 20%.
2. Next we found certain places in clock logic where we could make improvements in the slew values that also had an impact on a large number of paths. But we had already used the best drive strength cells out of the allowed library cell list for clock tree synthesis. So we had to pick clock cells from dont_use cell list. These high-drive strength cells are normally masked out and isolated during the fabrication process because they have EM (Electro-migration) issues that ruled out their use in the active portions of the chip. This is a problem inherent to the aluminum interconnect used at the 180 nm node. But we carefully selected a few of these rejected higher drive cells that we thought could help us in our timing and performed extensive SPICE () simulations on them over a load/slew range that made us confident that they did not violate EM limits. We only had to do this at a handful of locations on the chip and it helped reduce TNS/WNS by a good margin.
3. Timing & Congestion aware multi-step routing:

Routing Critical Nets First: We developed an in-house script to identify nets with bad slews and high net lengths amongst the top violating paths after routing. The script also calculated number of hops/segments in the net that were part of the net to assist in making judgments on the worst hit nets. The output of the script is shown in Table 1:

These nets were then routed before signals clocked with higher weight. Also, to avoid hopping, signal integrity (SI) aware routing was avoided. The nets thus routed were set as fixed-nets so that eventual routing runs would not mess up their topology.

Routing Clock Nets: Clock nets with weights less than the above critical nets were then routed with no detouring. However, the clock nets were not set as fixed and so were modifiable as conditions dictate.

Routing other nets: The rest of the nets were routed normally without setting special weight and detouring parameters.

The resulting routing topology after fixing is shown in Figure 3:


Click on image to enlarge.

Conclusion:
Because the pre-route engines used in current EDA tools are tuned for the smaller geometry technology nodes (90nm and below), they are not very good at assessing the metal trace hopping or detours that are necessary at higher 180 nm nodes. So, it should not come as a surprise that designs done in more conservative 180 nm resistive technologies might throw up roadblocks when it comes to closing the timing at the PostRoute stage. So when implementing circuits at the more conservative 180 nm node, designers need to be extra careful when the EDA tool’s trial route engine reports something you might have safely ignored at the smaller geometry 90 nm technology nodes. In such cases it would be advisable to follow the proactive approaches described in this article if you want to avoid last minute surprises.

Abbreviations used in the article
EDA: Electronic Design Automation
DFM: Design for Manufacturability
MCU: Micro Controller Unit
CTS: Clock Tree Synthesis
SoC: System on Chip
TNS: Total Negative Slack
WNS: Worst Negative Slack

Mayank Verma is a Sr. Design Engineer at Freescale Semiconductor, Noida, India. He has 5 years of rich industry experience in the fields of SOC Placement, CTS, Routing, Noise, Timing, DRC and DFM Closure. He has worked on complex low power complex automotive and Industrial SOC at multiple technology nodes.

Vijay Bhargava is Lead Engineer at Freescale Semiconductor Noida. In his career spanning 10 years, he has worked extensibly on Soc and Block-level Verification, Owned Digital IPs, Soc-Integration, Power Estimation/Modeling and DSP Architectures in Front-End. As for backend, he has handled Synthesis and APR activities. Currently he is leading timing closure activities for SoCs.