Streamlining design using macro placement algorithms in mixed signal SoCs
Comparison and Results
Optimum floorplan
In order to get an effective SoG area, hard macros need to be placed in carefully in an organized way. During the initial phase, most designers do not consider obstructions in all metal layers, and try to come up with the best floorplan based on timing and connectivity instead. But unfortunately this is not the best floorplan. As shown in Figure 4(a), most of the topmost metal layer (AP - ALCAP Layer) blocked in block0, block1, and block3 are placed at top side of die, which restricts the power distribution from power pads to SoG. By going with this floorplan, power distribution is through the channel between the AP blockages, which is lesser, and ends up eating more resources for power to meet the specification or requires change in power pad location when identified at a later stage.
Using the proposed algorithm designer comes up with the optimum floorplan as shown in Figure: 4(b) by flipping the macros in place at the initial design cycle phase based on routing obstructions (besides meeting timing and connectivity requirements). This will achieve the same specifications using fewer metal resources as the channel for topmost metal layers is increased for power distribution, which will pay off in die size. Since we have more resources in the top layer, we will have less IR drop.
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Better IR Drop
Using the conventional method for floorplanning resulted IR drop numbers are 80mv (VDD+VSS) because of lesser channel as shown in Figure 5(a). The proposed algorithm enables 47.5 % improvement in IR drop and the numbers for VDD+VSS will be reduced to 42mV, as shown in Figure 5(b).
Click on image to enlarge.
Conclusion
The proposed SMP algorithm enables die size reduction, which leads to higher gross margins. It also results in improving IR drop and routing-friendly design. This Algorithm covers the risks of floorplan change at a later phase of the design cycle.
Gurinder Singh Baghria is a Design Engineer at Freescale Semiconductor, India Pvt Ltd. He is mainly responsible for SoC Physical design activities. Floorplanning, power planning/estimation and IR drop analysis (Static/Dynamic) are his main expertise and focus areas. Received B.Tech degree in Electronics instrumentation and control from the Thapar University.
Sonal Ahuja is a Senior Design Engineer at Freescale Semiconductor, India Pvt Ltd. She is mainly responsible for SoC backend flow physical Integration activities. Floorplanning, power planning/estimation, padring integration and IR drop analysis (Static/Dynamic) are her main expertise and focus areas. Received B.Tech from Thapar Universiity in Electronics communication.
Rishi Bhooshan is a SMTS (Senior Member of Technical Staff) at Freescale Semiconductor, India Pvt Ltd. His expertise is in the area of physical design, chip design tools, flows, and methodology, including design methodology such as low power design, power integrity and signal integrity, ESD/EMC, and reliability.
Sumit Varshney is a Senior Signal integrity Engineer at Freescale Semiconductor, India Pvt Ltd., specializing in package and PCB design analysis. His focus area is robust implementation of high-speed design interfaces such as DDR, PCI, and USB on package & boards. He received M.Tech from IIT-Delhi in opto-electronics and optical communication.
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