Streamlining design using macro placement algorithms in mixed signal SoCs
Addressing a problem in automotive SoCs where embedded flash and other memory take up half of the die area, the authors describe a smart macro placement algorithm they developed to deal with signal and power routing through memory segments that are partially blocked due to noise sensitivity.
In SoCs (systems on chip) used for automotive applications, embedded flash/memories take up almost 50% of the die area; the rest of the area is used for SoG (Sea of gates). To deal with signal routing, memories are totally blocked in all layers and power routing is partially blocked because the memories are sensitive to noise.
Placing such blocks is a knotty task because to avoid die wastage it must be accomplished with minimum routing channels. Currently there is no tool available to do automated macro placement intelligently considering data flow diagram (DFD), timing, and routability. As a result, manual placement of hard macros is a must to come up with a routing friendly floor plan. This process, being iterative, eats up huge cycle time and affects the die size estimate.
In this paper, we propose a SMP (smart macro placement) algorithm for reducing die size, improving IR drop, and reducing cycle time. The proposed SMP algorithm covers the following key points:
- In-place flipping of macros, based on internal cell blockages to decide the best orientation
- Checks all possible orientations that may be missed manually
- Outputs the best orientations in one go, thus saving on iterations and cycle time
Data flow diagram
The data flow diagram (DFD) describes the physical design flow, which is the sequence of activities performed for SoC physical design closure. The DFD has the following steps:
Data Preparation: In the Initial phase, setup and scripts are prepared for a design.Figure 1 shows a conventional physical design flow. Conventional flow has much iteration between placement and floorplanning for final closure of the design. Figure 2 shows the appropriate place for the algorithm in the physical design flow. The proposed algorithm gives the best possible macro placement in one go for efficient floorplan, which saves on the number of iterations required between floorplanning and the placement phase and results in saving cycle time.
Planning Phase: This phase has a major role in SoC success; proper planning needs to be done in order to avoid surprises at a later stage. The Planning Phase covers padring planning, design planning (hierarchical/flat), power planning, die size planning and macro selection.
Integration phase: In the Integration phase, placement of hard macros is finalized for timing and routability.
Placement and Timing phase: Standard cell placement is done in this phase, and needs to be in sync with hard macro placement for timing closure.
Final phase: Physical verification activities like DRC and LVS have to be done in this phase before final GDSII is shipped for fabrication.
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The SMP algorithm emphasizes in-place flipping of an instance to get the best possible orientation for each hard macro used in the design. This will make for better routability and better IR drop. The algorithm mainly focuses on the routing obstructions over the hard macros. Routing obstructions will lead to a resource crunch at a later stage of design if not planned properly during the planning phase of the DFD, which will then require an increase of the die area. This algorithm reads the LEF files of the hard macros to get the exact routing obstructions in all metal layers. Then, based on the raw or first cut floorplan, this algorithm intelligently decides the best possible orientation for all the hard macros in the design at the initial phase of the design cycle. Figure 3 describes the flow diagram for the SMP algorithm.
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