Design Con 2015

Static timing analysis: bridging the gap between simulation and silicon

Naman Gupta and Rohit Goyal, Freescale Semiconductor, Noida, India

December 04, 2013

Naman Gupta and Rohit Goyal, Freescale Semiconductor, Noida, IndiaDecember 04, 2013

Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is often misconstrued to be a magical solution to the meet timing requirements. While it is undoubtedly the responsibility of STA engineers to close the timing, it is equally important for the register transfer level (RTL) designers to avoid some conspicuous errors, which we refer to as architectural pitfalls for timing.

In this article we discuss AND-gate clock gating and OR-gate clock gating use cases, some obvious and some not-so-obvious, which can serve as a guide to designers to ensure that such situations are avoided upfront in the RTL stage and thus preclude the reiteration of timing closure activities from, let’s say, clock tree synthesis (CTS) and back to logical synthesis.

We conclude the paper with a case study of an odd-frequency divider circuit that has one implementation that yields correct results in RTL simulation and the necessary changes in the algorithm to ensure that it works well on silicon.

Clock gating
Clock gating is an integral architectural method to save dynamic power. While the backend tools are aware of the power dissipation, it is nevertheless a good design practice to insert clock gating cells upfront in the RTL. That’s because insertion of clock gating cells depends on the use cases and the intent. For example, if a clock gating either feeds a small number of flip-flops or feeds the clock to a critical IP which is expected to be operating most of the time, it makes little sense to add clock gating cells.

Clock gating cells incur additional dynamic power and area overheads, and designers must be aware that clock gating cells must only be done when the savings are expected to be more than the overhead. Apart from clock gating cells, sometimes simple gates like AND, OR, and NAND can also be used for clock gating. But these have eccentric timing requirements, and therefore it is necessary for RTL designers to use these cells discreetly after understanding the timing scenarios.

AND gate-based clock gating (Figure 1) is an example of AND gate-based clock gating. One input of the AND gate acts as the signal enabler, which is generally the output of a register. Another input is the clock. When the enable signal is 1’b1, the AND gate becomes transparent for the clock. However when the enable signal is 1’b0, the AND gate is ‘off’ and the clock is ‘gated’. While this circuit would work well in RTL simulations, in presence of delays that are discerned only during the backend phase of SoC design, the waveforms in Figure 1 show the potential issue of glitch at the output of the AND gate.

This places a constraint on the enable signal that it should change only during ‘low’ period of the clock. The problem could be solved if the register generating the enable was a negative edge-triggered flip-flop. While replacing this flip-flop with a negative edge-triggered flip-flop would solve the timing issue, doing so would alter the intended functionality of the circuit.


Figure 1: Potential issue with AND-based clock gating

OR gate-based clock gating (Figure 1) shows the usage of OR-Gate based clock gating. One input of the OR gate acts as the enable signal, which is generally the output of a register. Another input is the clock. When the enable signal is 1'b0, the OR gate becomes transparent for the clock.

However, when the enable signal is 1'b1, the OR gate is ‘off’ and the clock is ‘gated’. While this circuit would work well in RTL simulations, in the case of delays that are discerned only during the backend phase of SoC design, the waveforms in Figure 2 show the potential issue of a glitch at the output of the OR gate.

This places a constraint on the enable signal that it should change only during ‘high’ period of the clock. The problem could be solved if the register generating the enable was a positive edge triggered flip-flop. Just like the case with AND-gate based clock gating, while replacing this flip-flop with a positive edge-triggered flip-flop would solve the timing issue, doing so would alter the intended functionality of the circuit.


Figure 2: Potential Issue with OR-based clock gating


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