Using Smart I/Os to build pin-level digital logic functionality and reduce CPU loading


July 05, 2016

TanmoySen_CypressChethan_Devaraj,-July 05, 2016

Engineers working on system design often face the need to implement pin-level digital logic on input and output signals. For example, systems engineers working on clock propagation through a microcontroller often need to create clock trees, replicate an input clock into several buffered instances (with appropriate driving capabilities), and/or invert clock polarity. There are numerous other examples in which systems engineers have to implement combinatorial logic on the output or input signals. The option they usually have is to implement these last-minute changes using external components such as discrete combinational logics and “blue wires” to connect these components. This not only inflates the bill-of-material cost but also involves time-consuming PCB spins.

Figure 1. MCU + Discrete Logic ICs (Source: Cypress Semiconductor)

With the rapid growth of battery-operated devices, power consumption has become a major concern for systems engineers. Every bit of energy saved adds longevity to the battery before it has to be charged. Therefore, systems engineers try to offload the CPU – one of the most significant contributors to the total power – by implementing some simple I/O signal-processing tasks in hardware. For example, multiple breathing LEDs can be implemented by using XOR gates with two pulse-width modulated signals as inputs and the I/O port as output. The two pulse-width modulated signals should have slightly different frequencies; the beat frequency is the desired breathing rate of the LEDs. This scheme saves the CPU from turning ON at regular intervals, which would have been the case had this logic been implemented in firmware.

Figure 2. Hardware Implementation of 8 Breathing LEDs (Source: Cypress Semiconductor)

Today, microcontrollers are available that offer programmable logic on I/O ports for integration of board level glue logic IO functionality such as AND, OR, and XOR gates. Figure 3. shows how such a Smart I/O block might be integrated. The Smart I/O block is positioned in the signal path between the MCU’s Peripherals (such as TCPWM, UART and SPI) and the I/O port. Inputs to the chip from the I/O port can be logically operated upon before being routed to the MCU’s peripherals and connectivity of the chip. Likewise, outputs from the peripheral blocks and internal connectivity of the chip can be logically operated upon before being routed to the GPIO port. The Smart I/O block can operate even when the device is in low-power modes and can wake up the chip using the port interrupt, when required.

Figure 3. Example of Smart I/O in a microcontroller (Source: Cypress Semiconductor)

Components of Smart I/O block
Each Smart I/O block is associated with a specific port and can operate on the signal coming from or going into that specific port. In the case of the PSoC 4 from Cypress, for example, the Smart I/O block is composed of eight 3-input Look-Up Tables (LUTs) with an interconnection matrix as shown in Figure 4.

Figure 4. Smart I/O LUTs (Source: Cypress Semiconductor)

Smart I/O offers flexibility for interconnection using the interconnection matrix. Users need not write any code to configure the Smart I/O block. The MCU design tool chain, in this case PSoC Creator, simplifies the configuration of the Smart I/O block using a graphical user interface.

The input signals to the LUTs and the output signal from the LUT can be easily routed by selecting the dropdown list in the GUI. The Smart I/O LUTs truth table can be configured by specifying the output value for all the possible input combinations as shown in Figure 5.

Figure 5. Configuring the Smart I/O LUTs in PSoC Creator (Source: Cypress Semiconductor)


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