The definitive guide to ARM Cortex-M0/M0+: Wake-up operation

Joseph Yiu

September 14, 2016

Joseph YiuSeptember 14, 2016

Editor's Note: In designing deeply embedded systems, engineers face ongoing tradeoffs between power and performance. The rapid emergence of opportunities for personal electronics, wearables and Internet of Things (IoT) applications only exacerbates challenges in reducing power while enhancing performance. The ARM Cortex-M0 and Cortex-M0+ processors have emerged as a leading solution, providing the core for a broad range of microcontrollers designed to meet tough requirements for low-power, high-performance operation. In The Definitive Guide to ARM® Cortex®-M0 and Cortex-M0+ Processors, 2nd Edition, Joseph Yiu offers a comprehensive view of these processors. As Embedded.com blogger Jack Gannsle wrote, these books will "...give you the insight you need to be productive on real projects."

 

CHAPTER 9. System Control and Low-Power Features (Cont.)

9.5.4 Wake-up Conditions
When a WFI instruction is executed or when the processor enters sleep mode using the Sleep-On-Exit feature, the processor stops instruction execution and wakes up when an (higher priority) interrupt request arrives and needs to be serviced. If the processor enters sleep in an exception handler, and if the newly arrived interrupt request has the same or lower priority as the current exception, the processor will not wake up and will remain in pending state. The processor can also be woken up by a halt request from debugger, or by a reset.

When the WFE instruction is executed, the action of the processor depends on the current state of an event latch inside the processor:

  • If the event latch was set, the event latch will be cleared and the WFE completes without entering sleep.

  • If the event latch was cleared, the processor will enter sleep mode until an event takes place.

An event could be any of the following:

  • an interrupt request arriving which needs servicing

  • entering or leaving an exception handler

  • a halt debug request

  • an external event signal from on-chip hardware (device specific)

  • if the SEVONPEND (Send-Event-On-Pend) feature is enabled and a new pending interrupt occurs

  • execution of the SEV (Send Event) instruction

The event latch inside the processor can hold an event which happened in the past, so an old event can cause the processor to wake up from a WFE instruction. Therefore usually the WFE is used in an idle loop or polling loop as it might or might not cause entering of sleep mode.

WFE can also be woken up by interrupt requests if they have a higher priority than the current interrupt’s priority level, or when there is a new pending interrupt request and the SEVONPEND bit (Send event on pending) is set. The SEVONPEND feature can wake up the processor from WFE sleep even if the priority level of the newly pended interrupt is at the same or lower level than the current interrupt. However, in this case, the processor will not execute the interrupt handler and will resume program execution from the instruction following the WFE.

The wake-up conditions of the WFE and WFI instructions are illustrated in Table 9.13.

Table 9.13: WFI and WFE sleep wake-up behavior  

The wake-up behavior of Sleep-On-Exit is same as WFI sleep.

Some of you might wonder why when PRIMASK is set, it allows the processor to wake up but without executing the interrupt service routine. This arrangement allows the processor to execute system management tasks (for example, restore clock to peripherals) before execute the interrupt service routine, as shown in Figure 9.8.


Figure 9.8. Use of PRIMASK with sleep.  

In summary, the similarities and differences between WFI and WFE are shown in Table 9.14.

Table 9.14: WFI and WFE comparisons  

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