The definitive guide to ARM Cortex-M0/M0+: Ultralow-power designs

Joseph Yiu

September 28, 2016

Joseph YiuSeptember 28, 2016

Editor's Note: In designing deeply embedded systems, engineers face ongoing tradeoffs between power and performance. The rapid emergence of opportunities for personal electronics, wearables and Internet of Things (IoT) applications only exacerbates challenges in reducing power while enhancing performance. The ARM Cortex-M0 and Cortex-M0+ processors have emerged as a leading solution, providing the core for a broad range of microcontrollers designed to meet tough requirements for low-power, high-performance operation. In The Definitive Guide to ARM® Cortex®-M0 and Cortex-M0+ Processors, 2nd Edition, Joseph Yiu offers a comprehensive view of these processors. As Jack Gannsle wrote, these books will "...give you the insight you need to be productive on real projects."


CHAPTER 19. Ultralow-Power Designs

19.1 Examples of Using Low-Power Features

19.1.1 Overview
More and more chip designers are using the ARM® Cortex®-M0 and Cortex-M0+ processors in wide range of ultralow-power (ULP) microcontrollers and System-on-Chip products. In Section 2.6.1 (Chapter 2) we have already covered the low-power benefits of the Cortex-M0 and Cortex-M0+ processors, and then in Chapter 9, we have also covered the low-power features of the Cortex-M0 and Cortex-M0+ processors. Here we will go into more details of how to utilize various features, and what we should be aware of when creating low-power applications.

Before we start going into the details, a key point that software developers need to understand is that low-power features are very device specific. What we illustrated in the examples here is not sufficient to enable the software developers to get the longest battery life. Software developers should refer to application notes or examples from microcontroller vendors to utilize the low-power features available.

19.1.2 Entering Sleep Modes
By default, the Cortex-M0 and Cortex-M0+ processors support a sleep mode and a deep sleep mode. However, please note that microcontroller vendors can define additional sleep modes using device-specific programmable registers. Inside the processor, the selection between sleep mode and deep sleep mode is defined by the SLEEPDEEP bit in the System Control Register (Table 9.9).

For the users of CMSIS-compliant device driver library, the System Control Register can be accessed by the register symbol “SCB->SCR.” For example, to enable deep sleep mode, you can use:

SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /∗ Enable deep sleep feature ∗/


The System Control Register must be accessed using a word size transfer.

The actual differences between normal sleep mode and deep sleep mode on a microcontroller depend on the chip's system level design. For example, normal sleep might result in some of the clock signals being switched off, while deep sleep might also reduce voltage supplies to the memory blocks and might switch off additional components in the system.

After selecting the sleep mode, you can enter sleep mode using either the WFE (Wait-for-Event) or WFI (Wait-for-Interrupt) instructions. It is recommended to add a DSB (Data Synchronization Barrier) instruction before executing WFI/WFE to allow better portability (e.g., in other high-performance processors, there could be outstanding memory transfers that need to be completed before entering sleep).

In most cases, the device driver libraries from microcontroller vendors contain functions to enter low-power modes that are customized for the corresponding microcontrollers. Using these functions will often help achieving the best level of power optimization for the microcontrollers.

However, if you are developing C code that needs to be portable between multiple Cortex-M microcontrollers, you can use the following CMSIS functions to access WFE and WFI instructions directly (Table 19.1).

Table 19.1: CMSIS intrinsic functions for WFE and WFI instructions

For users that are not using CMSIS-compliant device drivers, you can use intrinsic functions provided by the C compilers, or using in-line assembly to generate the WFE and WFI instructions. In these cases, the software code will be tool chain dependent and less portable. For example, Keil® MDK-ARM and ARM DS-5™ provides the following C intrinsic functions (unlike the CMSIS version, they are in lower cases) (Table 19.2).

Table 19.2: Keil® MDK or ARM® DS-5 intrinsic functions for WFI and WFE

From architecture point of view, a DSB instruction should be executed before executing WFE or WFI. This ensures that outstanding data memory operations (e.g., buffered write) are completed before entering sleep. However, on existing Cortex-M0 and Cortex-M0+ processor, omitting the DSB instruction does not cause any issue.

Since the WFE can be woken up by various sources of events, including event occurred in the past, it is usually used in an idle loop. For example:

while (processing_required()==0) {

    __DSB();// Use of memory barrier is recommended for portability




Users of assembly programming environments can use WFE and WFI directly in their assembly codes.

Continue to the next page >>


< Previous
Page 1 of 3
Next >

Loading comments...