The definitive guide to ARM Cortex-M0/M0+: Low-power benchmark setup

Joseph Yiu

December 06, 2016

Joseph YiuDecember 06, 2016

Editor's Note: In designing deeply embedded systems, engineers face ongoing tradeoffs between power and performance. The rapid emergence of opportunities for personal electronics, wearables and Internet of Things (IoT) applications only exacerbates challenges in reducing power while enhancing performance. The ARM Cortex-M0 and Cortex-M0+ processors have emerged as a leading solution, providing the core for a broad range of microcontrollers designed to meet tough requirements for low-power, high-performance operation. In The Definitive Guide to ARM® Cortex®-M0 and Cortex-M0+ Processors, 2nd Edition, Joseph Yiu offers a comprehensive view of these processors. As Jack Gannsle wrote, these books will "...give you the insight you need to be productive on real projects."

 

CHAPTER 19. Ultralow-Power Designs (Cont.) 

19.7.5 The Test Setup

The overview of the setup can be summarized as:

  • MCG running in BLPE (Bypassed Low-Power External) state. External crystal oscil- lator running at 8 MHz is used with PLL and FLL disabled and bypassed.

  • For first step of our experiment, the microcontroller uses Normal Run and Normal Stop. The system runs on 8-MHz clock frequency.

  • Then we enhance the design to use Very Low-Power Run (VLPR) and Very Low-Power Stop (VLPS) modes to further reduce the power.

  • The wake-up source selected is the Low-Power Timer (LPTMR) module.

  • UART0 is used and is configured to run at 38,400 bps.

The setup of the MCG is easy. The control code is already included in the default. "system_MKL25Z4.c". We only need to select the define option in this file: 

The code to get the system running is as follows. Please note that at the start of the test program, a UART input function is called so that the test does not start until it has received a character from the UART interface. This prevents the board from being locked out completely by the low-power mode and allow the program flash to be reprogrammed (see safe mode operation in 19.5.2).

Once this is working, the "void Low_Power_Config(void)" function is updated to include the additional enhancement:

  • To enable the use of VLPR and VLPS modes, we need to reduce the clock frequency of the system from 8 MHz to a lower frequency at 4 MHz or lower. A frequency value of 1 MHz is selected.

  • To save more power, the flash memory is turned off during sleep (this is referred as Flash Doze feature in Freescale document).

  • Turn off internal oscillator.

  • Enable the very-low power modes by programming to the System Mode Controller (SMC) module.

The modified “void Low_Power_Config(void)” function is as follows.


 

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