Using model-based design in signal integrity engineering

Colin Warwick, The MathWorks

August 1, 2007

Colin Warwick, The MathWorks

RF techniques, originally developed for wireless communication projects, are being repurposed to solve the increasingly complex problem of preserving signal integrity in high-speed data transmission between chips joined by backplanes and printed circuit boards. These pin-to-pin connections are becoming mini-communication systems in their own right. In parallel, Model-Based Design is being adopted for these projects to significantly speed the design process, through a graphical environment with prebuilt, optimized algorithms and blocks. This article addresses the convergence of these two trends.

Planning a typical application
We'll use Model-Based Design and RF techniques to create an impairment model of the backplane that is used as a test environment in both the modeling and design phases for the development of mitigating algorithms.

The first step is to use a vector network analyzer (VNA) to measure the frequency-domain response of the backplane and record it in an S4P (four-port) Touchstone file. Modified rational functions are then used to fit the frequency domain data to a time-domain behavioral transfer function. The resulting transfer function is used as a test environment in the development of mitigating algorithms in a Simulink® model. A Verilog-A version of the transfer function is generated for verification of the circuit design. The circuit design can be based on the model and completed using electronic design automation (EDA) tools.

Signal integrity challenges
The increasing speeds used in telecommunication and data communication infrastructures have made it more difficult than ever to achieve data transmission at sufficiently low bit error rates (BERs). A signal sent from a gigabit per second transmitter on the I/O pin of one chip travels first along a trace on a plug-in card, then across a backplane to another plug-in card that contains the receiving chip. The signal often becomes degraded by intersymbol interference (ISI), frequency-selective attenuation, and crosstalk. The ISI impairment is caused by reflections, typically caused in turn by impedance mismatch at various interconnection discontinuities. These impairments become more severe as the data rate increases. By contrast, when data rates are below 1 Gb/s, we can rely on a fairly flat backplane frequency response. Also, the echoes of previous pulses decay before the next one comes along, so ISI is less of an issue.

Today, data rates are usually well above 1 Gb/s, so the echo decay time is longer than the pulse spacing, and the received pulse is mixed up with echoes of the previous pulse. The job of signal integrity engineering is to mitigate this and other impairments. Design of adequate mitigating algorithms, such as a pre-emphasis filter for the transmitter and a decision feedback equalizer (DFE) for the receiver, requires an accurate model of the impairment.

The fact that the backplanes and the chips with the I/O transceivers are produced by different companies increases the complexity of the design process. In order to facilitate a dialog between these two groups, equipment manufacturers develop behavioral models of the backplane. Semiconductor companies use these models as a test environment for transceiver design. Chip companies furnish behavioral models of the I/O design so that backplane makers can check the range of backplane designs in which the transceiver can operate successfully. The design process naturally involves a fair amount of iteration because when the equipment manufacturer changes a design it may change the test environment for the chip maker and vice versa. The companies involved typically go back and forth modifying their designs and models until the complete system meets performance specifications.