Consolidation is a long-standing trend within the embedded world. It enables more capable, higher-performance embedded devices using fewer components, at lower cost and power budgets.

The latest round of this trend is the proliferation of multicore embedded microprocessors, offering multiple processor cores in a single package " with lower power consumption and cost than an equivalent single-core processor.

Taking advantage of multiple processor cores will require more system-level design cooperation between software and hardware teams. In that spirit, here are high-level overviews of three simple models for multicore systems which are straightforward to implement with today's tools and hardware.

These multicore design patterns are not intended to be rigid models for exactly specifying a system. Rather, they are starting points for thinking and talking about the high-level picture of what your system does, and provide a common terminology so that hardware and software teams can hash out a multicore system structure.

Planar Pattern
The first pattern is the Planar Pattern, named from the "control planes" and "data planes" which typically divide a telecommunication system's processing tasks. Shown in Figure 1 below, it is an example of a broad and diverse category of multicore designs, collectively called Asymmetric Multiprocessing (also "AMP" or "ASMP").

Figure 1: The first model is the Planar Pattern, named from the "control planes" and "data planes," which typically divide a telecommunication system's processing tasks.

To use the Planar Pattern, your system needs to be divisible into self-contained pieces that have significantly different processing requirements.

In its classic telecom and media processing forms, this pattern's advantage comes from running data-heavy algorithms on a specialized DSP or network processor, while keeping the rest of the system software on a general-purpose CPU.

This specialization means that Planar Pattern systems are normally implemented on purpose-built hardware " the high-level design of software for a Planar system will usually follow from the structure of the hardware it runs on. As many Planar hardware devices have only one general-purpose CPU core, conventional single-core tools, operating systems, and design techniques can be used for design and debug of the general purpose side of the system.

Grid-on-Chip Pattern
The Grid-on-Chip (or just "Grid") Pattern (Figure 2, below) is a variation of the Planar Pattern, and covers any multiprocessor system made up of a collection of fully independent, networked nodes. The Grid is the on-chip version of the office computer network " a collection of networked processing nodes that share physical proximity, but are otherwise independent. Some literature refers to this type of system as a distributed multiprocessing system, and it is also lumped into the general category of AMP/ASMP systems.

Figure 2: The Grid Pattern is a variation of the planar pattern and covers any multiprocessor system made up of a collection of fully independent, networked nodes.

The key requirements to use the Grid Pattern are to first partition your system, and then find a suitable inter-node communication system. (Although more advanced Grid systems can be built to reconfigure themselves at runtime, designers of a Grid Pattern system need to carefully think through the assignment of system functions to processing nodes.)

Aside from the partitioning, Grid systems have the fewest high-level design constraints of these three design patterns. Once the system is partitioned, design and implementation of each individual node proceeds just like a standalone system. Grid systems can be implemented on specialized hardware, but another common choice is to create Grid nodes by using SMP hardware and dividing up the shared memory into per-core sections.

Grid Pattern systems have several important advantages over other designs. First, they easily integrate with legacy software " legacy systems can even continue to run intact on their own nodes within the Grid. In addition, Grid systems have advantages in determinism and debuggability.

The loose coupling of a Grid Pattern system design means fewer surprises regarding resource contention, and debugging is simpler because familiar single-core debug methods can be used for each system node in isolation. The partitioned nature of a Grid Pattern system leads to its strengths, but is also the source of its weakness " the partitions make it difficult to redistribute resources, which can make Grid systems less flexible for adapting to future, unanticipated requirements.