Designs using PCI Express--for all the performance bang that comes from its 2.5 GT/s (gigatransfers per second) in Gen 1 and 5GT/s (Gen 2) speeds--usually address one target at a time. This means an identical write packet needs to be sent to two addresses sequentially, instead of simultaneously--a process that tends to exact a penalty on system throughput.

To counter this, the use of dual-cast techniques allow a PCI Express switch to make a copy of a posted write packet and send it to a second address, saving the original source the trouble of transmitting the same data twice, to two different locations.

Dual casting enhances performance in applications where data must be copied simultaneously to multiple locations within a PCI Express fabric--essentially doubling throughput between the originating source and the target addresses. Designers can implement dual casting to eliminate an unnecessary step and help boost system throughput--and get a little "free bandwidth" out of it.

Table 1 shows the standard type of system read and write cycles allowable in PCI Express. The transaction layer packets, or TLPs, are the payloads that communicate information between source and destination. It is this exchange of data back and forth for which the operating system executes work across the system.

Of the message types available in PCI Express, only a memory write and a message are posted transactions, which are a communication sequence for which no return action is required by the recipient. For example, a system message, such as a surprise error event, is a transaction for which the initiator can or will inform the target, but for which the initiator doesn't expect a return message; the initiator might no longer be functional so as to accept any possible return message.

Similarly, a transaction for which the user simply wants to deposit information, such as a write to memory, doesn't require a system response. Today's memory systems are very robust; if the integrity of the packet presented to the memory device can be guaranteed, there is little need to read it back for comparison. (Note that PCI Express provides a separate mechanism, called a replay buffer, which ensures safe link-to-link TLP navigation.) Hence, writing to memory requires traffic flow in one direction, with no requirement for a return action.

Non-posted transactions
In contrast, a posted transaction is one that requires a response by the recipient. A memory read is a request for a return of information. TLPs flow in both directions; the initiator first issues a read request and the memory then returns the requested information. The completer is obligated to "complete" the request. Interestingly, a read completion can be with or without data, depending on the request.

As noted in Table 1, two basic types of transactions perform system reads or writes: memory cycles or IO cycles. The use of IO cycles has a history in legacy (conventional PCI) devices. Conceptually IO reads and writes are targeted at registers typically within an IO device. An IO write will load a value within a register, then return a completion confirming delivery. IO writes are implicitly atomic transactions and are not the preferred means of high-bandwidth data delivery.

While IO reads and IO writes are part of the standard, usage of these mechanisms is really the result of legacy endpoint devices. PCI Express encourages the use of a memory write over an IO write because it is twice as bandwidth-efficient compared with the legacy approach. That said, PCI Express still maintains the ability to generate IO read and IO write cycles, and the compatibility to legacy PCI operation (through the use of a PCI Express-to PCI bridge).