Historically, memory coherence in multiprocessor systems was often achieved through bus "snooping," where each core was connected to a common multitier bus and was able to snoop on memory-access traffic of processor peers to regulate the coherence status of individual cache lines. For that, each core maintained the coherence status of L1 cache lines locally and posted status changes to peers via the common bus.

The increasing size and complexity of the system-on-a-chip (SoC) led to restructuring of the multitier-bus philosophy in favor of localized point-to-point connections with centralized traffic routing. This configuration enabled speed and power improvements on now localized bus segments due to reduced load and segment length. Also, bus-contention problems eased, and throughput increased for the localized data exchange. In response to this trend in system architecture, the Open Core Protocol (OCP) standard emerged to consolidate this design philosophy. Further, emergence of IP-provider business models catalyzed the standardization of IP interconnect and design methods to facilitate design reuse centered on an open standard.

However, localized bus transactions, as conducted through OCP interconnect segments, decouple processors throughout a multicore cluster. Coherence schemes cannot be directly based on bus snooping and reliance on bus arbitration to ensure access ordering. Different methods of communication are needed to ensure data is accessed consistently. Additional challenges arise in the ordering of competing L1-line data requests. One way to address these challenges is to add coherence-message communication to each processing element as depicted in Figure 1 in a system MIPS calls a Coherent Processing System (CPS). This system provides the means of snoop-type cache coherence.

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Coherence messages embody a new type of command within the OCP protocol. Members of the processor system send coherence messages toward a centralized coherence manager that provides access ordering (serialization) and message routing to provide snoop-type access to peer members. These peers will respond with their individual L1-line status and post a message response. Depending on responses, the coherence manager initiates data movement for coherent data among cores and funnels access toward higher-level memory hierarchies such as L2 and L3 caches. I/O coherence units also provide a means to phase-in/out data toward/from the coherent address space and are part of coherent-message exchange.