Failover
The reliability and redundancy of a system is extremely important in today's computing infrastructure. These MR switches offer two levels of redundancy or failover. In the normal PCIe switch mode, these devices offer an on-chip standard NT port that allows a secondary (active or passive) host device for failover.

In MR switch mode, 1+1 or N+1 failover capabilities are provided to support high availability and redundancy. In 1+1 failover configuration, two hosts are paired to provide either active-active (both hosts are active) or active-passive (one host is active while the other waits in standby mode until the primary host fails) failover capability. This can be repeated to create multiple 1+1 host failover ports, as illustrated in Figure 5 below.

Figure 5. Multiple 1+1 host failover ports

In N+1 failover mode, one host may be configured as (active or passive) backup for N number of hosts, as illustrated in Figure 6 below. The user can also configure a backup host for one host that has been designated as a backup host for the rest of the hosts to provide an additional layer of protection " essentially backing up your backup.

In both N+1 and 1+1 failolver, hosts exchange heartbeat and status information through mailbox or scratchpad registers designated for this purpose. Heartbeat and scratchpad registers are readable from both sides and they can be accessed as memory or I/Os.

These registers provide a mechanism to generate software controlled interrupts for the failover event generation. When failover occurs, the host port of the failing switch partition is disabled and its downstream ports are moved to the backup host's partition and a failover event interrupt is generated. The back-up host will then be able to enumerate the new downstream ports and associated endpoints.

Figure 6. In N+1 failover mode, one host may be configured as (active or passive) backup for N number of hosts.

It is important to note that while the failover mechanism is being executed with the MR switch, the other partitions of the switch continue to operate normally with no traffic interruption or status change. Also, the original downstream ports of the backup host will continue to operate normally while ports from the failing hosts are being moved from one host domain to the other.

Conclusion
As a result of the PCIe efforts of PLX and other silicon vendors, have enhanced system performance and reduced the acquisition and operating cost of embedded systems. With MR switches, these vendors have created a practical solution to address multi-host, fail-over, and IO sharing needs.

The industries and applications waiting for a full MR-IOV implementation do not have to wait any longer. Instead, they can start implementing key MR-IOV functions through MR switches today. These high-performance switches will allow system developers to service embedded systems' needs more effectively and efficiently than the traditional methods being used in today's systems.

Akber Kazmi is marketing director for PCI Express switching products at PLX Technology.