Making packet processing more efficient with network-optimized multicore designs: Part 3This "Product How-To" article focuses how to use a certain product in an embedded system and is written by a company representative.
To address some of the packet processing issues described in Part 1 and Part 2 in this series, it has become feasible from the performance as well as from the power consumption point of view to build complete packet processing applications using the general purpose Intel multicore architecture processors.
Architects and developers in the industry are now considering these processors as an attractive choice for implementing a wide range of networking applications, as performance levels that could previously be obtained only with network processors (NPUs) or ASICs can now also be achieved with multi-core Intel architecture processors, but without incurring the disadvantages of the former.
Implementing packet processing applications on the Intel multi-core processors enables the reuse of the extensive code base already developed for the Intel architecture processors including BIOS, all the major Operating Systems, libraries and applications. The same is true for the mature software development tools already in place for the Intel architecture processors.
Developing packet processing applications on Intel architecture would allow the reuse of the important assets of developer skills and knowledge base on the Intel architecture processors.
As opposed to NPUs, the software engineers are not required to learn a special purpose programming model and tools for packet processing; instead, they can continue to use the same architecture and tools they are comfortable with and are most productive with.
As opposed to NPUs which often use special purpose instruction sets, the IA processors have a general purpose architecture and instruction set, which represents the key advantage responsible for their programmability.
As result of this, the multi-core Intel' architecture processors allow the implementation of highly programmable control and data planes, with fewer constraints than the NPUs.
The multi-core Intel architecture processors offer scalability through software for the control and data plane processing, which is the way to go for networking applications relying on protocols and standards in a continuous evolution.
Unlike NPUs, the multi-core Intel' architecture processors do not rely on expensive resources that are difficult to scale up, like on-chip multi-port memory, CAM memory, large external SRAM memory, etc.