Making hardware more like software

Mario Khalaf and Ajay Jagtiani, Altera Corporation

May 27, 2011

Mario Khalaf and Ajay Jagtiani, Altera Corporation

Combined system and FPGA design portion
A tool that allows planning the proposed system along with the processor can connect the peripherals to the processors, map the address bus, control bus and data bus and create the system with a description of the system in HDL which will be then translated to the device in the place and route tool. This tool allows planning for the custom components or personas for each of the partial blocks. Figure 8 shows an example of a system with two top level implementations of the FPGA.


Click on image to enlarge.
One of the key requirements for this tool is to support features like design hierarchy, and incremental capabilities (not to be confused with the incremental flow described earlier). The primary reason to have hierarchy is to efficiently map the design on to the processor system and the FPGA portion. A tool that supports design hierarchy will be natural fit for such a device and work well with the FPGA design flow wherein the hierarchies will be marked as design partitions and assigned to a location on the FPGA die. The incremental nature of this tool will help in generation of the HDL based on changes. This allows the components that were generated again to be tracked while lowering the compile time for generating systems.

Users are always designing the complete system with considerations for the division between the implementation in soft logic (FPGA) or part of the hardened SoC. A tool that allows design of the entire system in one tool modelling simultaneously the hard and soft (FPGA) portion of the design is recommended. The FPGA portion and SoC portion should share the same memory map system, interrupts, and address space. Bus arbitration and bus alignment portions are automatically inserted by the system tool providing a single software development platform.

Figure 9 shows a tool flow chain. After completion through the system modelling tool, the software development for both the hard and soft processor using the software tool chain is done. The FPGA portion is then compiled through the system generator to generate the HDL for the bus and merge the HDL for the peripheral IP. The FPGA design software then compiles the HDL into multiple bit streams, one for each partial reconfiguration of the system.


Click on image to enlarge.
Once the HDL is generated it is then taken into the place and route tool for compilation. Since the system design flow has incremental capibilities to generate HDL, personas of Top 1 and Top 2 can always be created and new flavors of the system generated. Within Top 1 and Top 2, partial personas as shown in Figure 9: (Periph D1, D2, Periph E1, E2) can be created. The place and route tool will detect that either Top 1 or Top 2 have changed and compile the changed portion and generate a partial programming file. Similarly it can detect changes for D1, D2 and E1, E2.

The following are necessary steps for generating a programming file:

A.    To generate the base programming file:

1. Connect the system within the system tool.
2. Generate HDL for the system tool.
3. Instantiate the top level HDL for the entire design in the FPGA tool.
4. Designate partitions to the partial blocks and assign them to the location on the FPGA.
5. Compile the entire design. This is the base configuration of the FPGA.
6. Generate the programming file for the base configuration.
7. Program the device.

B.    To generate the partial images

1. Regenerate the new persona for Top 1 or Top 2 in the system tool (and for D1, D2, E1, E2)
2. Generate the HDL for the new components.
3. Recompile the design within the place and route tool. Since these were originally designated as partitions. This will happen incrementally.
4. Rest of the system uses the last compilation of the design.
5. Generate the partial programming files for the personas.
6. Program the device with the partial reconfiguration file.