Making hardware more like software

Mario Khalaf and Ajay Jagtiani, Altera Corporation

May 27, 2011

Mario Khalaf and Ajay Jagtiani, Altera Corporation

Summary of benefits
A single-chip architecture that combines the benefits of hard processors and FPGAs has been presented thus far. Although presented as a single-chip solution, it's important to note that the FPGA and the processor mimic some of the advantages of a multichip solution. In addition, the ability to reconfigure the FPGA through the processor partially and fully provides additional benefits especially when combined with a software device driver solution and a design tool chain that can model the entire system. Some benefits are:

• Partial reconfiguration saves area for peripherals (or cores) that do not operate simultaneously.
• FPGA bitstreams can be loaded remotely saving local flash space and providing security since no FPGA information is found on-board.
• A lower power core can be loaded into the FPGA for different operating modes without rebooting the embedded OS.
• A debug core can be added to FPGA to monitor traffic while other peripherals are running.
• Different acceleration algorithms can be added to the FPGA, if used as a coprocessor dynamically.
• System is upgradable, since all FPGA operation modelled in terms of software device drivers including configuration.
• Single tool-chain to manage the entire system.

Chain of tools
A hardware architecture and a software tool chain that combines the benefits of a hard-processor and an FPGA in an embedded system has been presented. Many embedded systems today use multiple chips in the same scenario. The addition of reconfiguration (full and partial) to the FPGA directly from the processor without the OS rebooting and without suspending the processor offers added versatility to the system. In addition, a single tool chain using a system modelling tool that simplifies the design of the complex embedded system has been proposed. 

Mario Khalaf is a principal investigator, Office of the CTO at Altera Corporation. Mario has over 15 years of experience in the FPGA industry. Mario is also one of the original software architects of the Quartus II system.

Ajay Jagtiani is a software technical marketing manager at Altera. He holds an MBA in financial analysis from the University of San Francisco, an MSEE from Stevens Institute of Technology and a BSEE from Bombay University.