Porting Embedded Windows CE 6.0 R2 to the OMAP-L138, Part 1
In this three part series, Artisom Staliarou and Denis Mihaevich describe in detail how they ported the Windows CE 6.0 R2 embedded operating system to the Texas Instruments ARM-based family of OMAP-L138 processors.
One of the most flexible implementations of the ARM architecture is Texas Instruments' OMAP-L138 SoC. With careful design it can be used not only as the basic core in mobile applications but is flexible enough to be used in a wide range of standalone non-mobile designs in industry, medicine, and machine automation.
This article describes our experiences developing designs based on the OMAP-L138 and the C6-Integra family in general. The embedded operating system we used was Microsoft Windows Embedded CE/Compact, a multicomponent real-time operating system (RTOS) that supports such architectures as ARM, MIPS, SH4, and х86. A developer with a board support package (BSP) for a specific platform can quickly create an operating system image by selecting necessary components.
A wide range of tools for debugging and profiling of the core code, user applications, automated driver test system (CETK), and OAL layer (OEM Abstraction Layer) are available for Microsoft Windows Embedded CE/Compact, as well as numerous helpful utilities for control and setting of the device hardware operations. Another strength of the OS is that it is possible to port a code from applications written for desktop versions of Microsoft Windows OS, which significantly reduces the time and costs for end device development.
The OMAP-L138 SoC
Texas Instruments' OMAP-L138 is a low-power, dual-core system-on-chip (SoC) that combines an ARM926EJ-S RISC MPU with a TI C674x VLIW DSP and includes a rich peripheral set.. These cores support floating point mathematical operations, and have a Programmable Realtime Unit subsystem (PRUSS) consisting of two 32-bit cores that allow off-loading of the ARM-core by performing preliminary data flow processing chores. Also, one of the PRU cores can be turned into a CAN-peripheral. The ARM926EJ-S core incorporates all of the necessary necessary internal modules for designing an application based on the Microsoft Windows Embedded 6.0 RTOS. A flow diagram for this SoC is shown in Figure 1.
Click on image to enlarge.
A useful feature of this SoC in embedded high performance applications is a multilevel central bus with an integrated enhanced direct memory access (EDMA) controller. This bus has internal links up to 64 bits in width that connect the peripheral with memory, making it possible to bypass the processor without the use of other bus links. This also makes it easier to resolve arbitration problems.
With this bus, the EDMA controller can not only transmit data not resident on the cores, but can perform general operations such as array sorting under hardware control. Another good addition to the rich peripheral mix is a video port and SATA interface with a transmission rate of up to 3 Gbit/s.
These features make it possible for developers to build SoC-based designs that efficiently capture, process, and store media content. The SoC contains an McASP audio interface (multichannel audio serial port) that receives and transmits data to devices via 16 independent channels. This latter feature lets designers implement such devices and functions as DVD-players, audio interfaces, and audio processors.
Board Support Package
Board Support Package (BSP) development is one of the most labor-intensive processes when building embedded systems based on an OS. Stable operation and quality of the final product are mainly determined by the quality of the BSP, so the developer needs complete knowledge of the SoC as well as detailed understanding of the operating system.
MPC Data (www.mpc-data.co.uk/windows-embedded/) provides a basic BSP for this SoC. It includes almost all drivers of peripheral units for this chip, core abstraction layer (OAL), and standard loader EBOOT. The OAL layer of this BSP supports:
- loading parameters (transmitted from the loader);
- start of the ARM-core cache (instructions and data cache, write buffers for Copy-Back mode);
- interrupt controller (full-function support with interrupts from primary inputs);
- dedicated timer for the OS (with 1 ms steps) - 32-bit timer 0 is used;
- program emulation of a real time clock;
- memory management unit (MMU) for the formation of a table of addresses translation from physical into virtual;
- input/output system control;
- core profiler (also timer 0 is used);
- output of debugging messages via UART2-port;
- Kernel Independent Transport Layer (KITL) via the EMAC network peripheral (with support of operation via interrupts or by method of continuous scanning) for core debugging;
- Virtual Network Miniport (VMINI) bridge for simultaneous operation of the core debugger and network adapter in the OS;
- SDK: a subroutine for access to the peripheral management , PLL and general purpose Input/output (GPIO) controllers;
- real time clock module (RTC);
- watchdog timer; and
- power management system with the support of the OEMIdle() idleness subroutine.
The BSP contains tests to be performed on all of the basic peripheral modules. Support of testing is implemented for the file system modules, input/output ports, and I2C/SPI buses via automated tests with the support of the open source KATO results-logging tool.
The support of KITL and VMINI allows debugging of new drivers and services of the already assembled unit with maximum convenience and speed, significantly reducing the time required for development.