Designing a DSP-based Digitally Controlled DC-DC Switching Power Supply
With digital signal processors (DSPs) getting some serious consideration for use in controlling power supplies, the embedded systems designer needs to address a number of pertinent factors in the design and implementation of a digital control loop. For one thing, accurate representation of the control blocks and the associated control parameters is critical for the analog designers in order to enable them to implement the DSP based digital control techniques using the well-known analog control design approaches.
But the result is well worth the effort. DSP based digital control allows for the implementation of more functional control schemes, standard control hardware design for multiple platforms and flexibility of quick design modifications to meet specific customer needs. DSP based digital control allows for the implementation of more functional control schemes, standard control hardware design for multiple platforms and flexibility of quick design modifications to meet specific customer needs.
Digital controllers are also less susceptible to aging and environmental variations and have better noise immunity. Moreover, modern 32-bit DSP controllers, such as TMS320F280x, with their real-time code debugging capabilities, give the power supply designers all the benefits of digital control and allows implementation of high bandwidth, high frequency power supplies without sacrificing performance [2-4]. The extra computing power of such processors also allows implementation of sophisticated nonlinear control algorithms, integrate multiple converter control into the same processor and optimize the total system cost.
However, the power supply engineers, mostly familiar with analog control design, are faced with new challenges as they start to adopt these digital control techniques in their designs.
This article describes a step-by-step DSP based digital control design and implementation of a high frequency dc-dc converter, illustrating two different approaches to digital control design: design by emulation and direct digital design.
The first method, namely design by emulation, allows the power supply designers to do the control design in the familiar s-domain and then convert it to a discrete/digital controller. The second approach known as direct digital design, allows digital controller design directly in z-domain.
Starting with a dc-dc buck converter and a given set of performance specification, it discusses different control blocks, different control design approaches and highlights the significant differences in designing control in the digital domain compared to the analog approach.
The two methodologies will be described in detail, first shown in MATLAB and then verified by experimental results. In this process the effects of sampling delay and the computation delay are also analyzed in MATLAB and then verified experimentally.
The DC-DC converter setup
Figure 1 below shows a simplified block diagram of a digitally controlled dc-dc converter interfaced to a TMS320F280x DSP controller, with processor speed up to 100MHz and enhanced peripherals such as a high resolution PWM module, a 12-bit A/D converter with conversion speed up to 160 nsec, a 32x32-bit multiplier, and 32-bit timers.
|Figure 1. TMS320F280x DSP based Digital Control of DC-DC Converter|
The system parameters used in this design are:
4~6V, Vout = 1.6V, Max output current Iout = 16A, RL
= 0.1 ohm (Minimum)
*Maximum output voltage (used for ADC signal scaling) Vomax = 2V
*PWM frequency fpwm = 250kHz; Voltage loop sampling frequency fs = 250kHz
*Output filter components, L = 1.0uH, C = 1620uF, RC = 0.004 Ohm
*Desired voltage loop bandwidth fcv = 20kHz
*Phase Margin = 45 deg, Settling time < 75uSec
As indicated in Figure 1 above, a single signal measurement is needed to implement the voltage mode control of the dc-dc converter. The instantaneous output voltage Vout is sensed and conditioned by the voltage sense circuit and then input to the DSP via the ADC channel. The digitized sensed output voltage Vo is compared to the reference Vref.
The voltage loop controller Gc is designed to make the output voltage Vout track the reference Vref and at the same time achieve the desired dynamic performance. The digitized output U of this controller provides the duty ratio command for the buck regulator switch Q1. This command output is used to calculate the appropriate values for the timer compare registers in the on-chip PWM module. The PWM module uses this value to generate the PWM output, PWM1 in this case, that finally drives the buck converter switch Q1.
|Figure 2. DC-DC Converter Digital Control Loop Sampling Scheme|
Figure 2 above shows one example of a digital sampling scheme using the DSP on-chip peripherals. The sampling scheme affects the digital controller design and, therefore, needs appropriate attention. PWM output frequency is set up by configuring one of the on-chip Timers, T1 in this case. In this example, T1 generates a dual edge modulated (symmetric), 250 kHz PWM output.
These timers have associated compare registers which are used to write the calculated duty ratio values. These values then get compared with the timer counter value in order to generate the PWM output. The time at which a newly written compare value affects the actual PWM output duty ratio is controlled by associated PWM control registers. In this example, the PWM control registers are set up such that a new value written in the compare register, changes the actual PWM output duty ratio at the start of the subsequent timer (T1) period.
Also, the ADC control registers are set up such that the AD conversion is triggered at the middle of the ON pulse of the PWM output. As soon as the conversion is complete, the ADC module is set up to generate an interrupt. The time delay between the start of AD conversion and this interrupt is shown in Figure 2 above, as Tadc. This time includes the AD conversion time and the processor interrupt latency.
Inside the interrupt service routine (ISR), the user software reads the converted value from the ADC result register, implements the controller and then writes the new PWM duty ratio value to the appropriate PWM compare register. However, this new duty ratio value takes affect at the start of the subsequent PWM cycle. From Figure 2, it is clear that the time delay Td, between the ADC sampling instant and the PWM duty ratio update, is half the PWM period. In this case, the PWM period and the sampling period (Ts) are equal and so the computation delay is, Td = Ts/2.
Also shown in Figure 2 above, the calculation of a new duty ratio value inside the ISR is completed well before a subsequent interrupt is generated. This means that, at this sampling frequency, the processor bandwidth (100 MHz) allows for sufficient spare time to extend the ISR and execute multiple controllers or other time critical tasks. Some of this spare time can also be used for non-time critical tasks by running them from a background loop.
Design by Emulation
In the Design by Emulation approach, also known as Digital Redesign Method, an analog controller is first designed in the continuous domain as if one were building continuous time control system, by ignoring the effects of sampling and hold associated with the AD converter and the digital PWM circuits. The analog controller is then converted to a discrete-time compensator by some approximate techniques.
Figure 3 below represents a simplified block diagram of the system in Figure 1. It shows all the different components of this closed loop control system in s-domain.
|Figure 3. DC-DC converter congrol loop block diagram in the s-domain|
The small signal power stage model of the buck converter in s-domain is indicated as Gp(s). For the given system parameters with Vin = 5.0V and RL = 0.1 ohm, this is derived as,
If the maximum output voltage is Vomax, then the voltage feedback factor is, Kd = 1/Vomax, provided that the digital output voltage Vo is represented in Q31 fixed-point format for this 32-bit DSP controller . The PWM modulator gain is Fm = 1. This is so because the user software together with the on-chip PWM hardware can be configured such that as the controller output U (in Q31) varies between 0 ~ 7FFFFFFFh, the PWM output duty ratio d varies between 0 ~ 1, .
For this plant Gp(s), a suitable analog controller Gc(s) can be designed in MATLAB using the available control design tool called 'sisotool'. The Bode plot for this design is shown in Figure 4 where the system bandwidth (BW) is set at 25 kHz with a phase margin (PM) of 71 deg.
|Figure 4: DC-DC converter control loop Bode Plot Gp(s) * GC1(s)*Kd*Fm (MATLAB)|
The corresponding controller Gc1(s) can be easily imported from the MATLAB control design toolbox. This is found as,
This analog controller Gc1(s) can be discretized by any of the commonly used discretization methods such as, Bilinear, Pole-Zero match and Forward etc. [5, 9]. This can be performed in MATLAB simply by writing the MATLAB script as:
This generates the following digital controller Gc1(z):
where, the sampling time is Ts = 1/fs = 4 microseconds. In discrete form, this controller is written as,
U(n) = 1.605U(n-1) - 0.605U(n-2) -12.34E(n) - 22.53E(n-1)_10.28E(n-2)
where, U is the control output and E is the error voltage. The quantities with (n) denote the sampled values for the current sampling cycle, the quantities with (n-1) denote one sample old values and so on.
This controller was implemented using the TMS320F280x DSP instruction set. During the code initialization the coefficients of the above controller are first converted to a suitable fixed point format (Q format) in order to get the best accuracy out of this 32-bit processor.The fixed point format used for the controller coefficients in this code example is Q26.
Once the controller was implemented in the DSP, its closed loop
dynamic performance was tested on a prototype dc-dc converter. This
transient load response is shown in Figure
|Figure 5. DC-DC Converter Load Transient Response (loop gain = Gp*Gc1*Fm*Kd)|
For a step load change of 15A, the output voltage settles within 30uSec (1% band). The converter has a satisfactory time response. However, the damping of the transient response does not reflect a phase margin of 71 deg as shown in MATLAB Bode plot (see Figure 4 earlier). This difference in the designed and actual phase margin is because of the fact that we completely ignored the effect of sampling and hold and the computation delay.
In the alternative digital control design method, the effect of these delays can be taken into account prior to the control design that results in a more predictable and accurate dynamic performance. This is described in detail next in Part 2: Direct Digital Design of a DSP based power supply.
As a member of the systems application team at Texas Instruments, Inc., Shamim Choudhury's main areas of interest have been on DSP based digital control of switch mode power supply, UPS and motor control systems. Prior to his joining TI, Shamim spent two years at Alcatel, and three years at International Game Technology, as a Design Engineer working on switch mode power supplies.
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