Managing mixed voltage interfaces between portable devices and memory cards

Prasad Dhon, Texas Instruments

September 25, 2007

Prasad Dhon, Texas Instruments

As portable applications become more feature-rich and smaller in form factor, power consumption becomes critical in a design.

Advancements in process technologies have allowed designers to take advantage of the latest processors that operate at lower voltages. However, the side effect of using lower-voltage processors is often a mixed-voltage system.

For instance, several processors have maximum I/O voltages restricted to 1.8V, with many of the peripheral devices continuing to operate at more traditional voltage nodes (3.3V).

This also holds true with most removable flash memory cards, which are often used in portable applications operating at 3V. To enable seamless communication between a low-voltage processor and a 3V memory card, a voltage level translator must be used for proper interfacing between the two devices.

Figure 1: Traditionally, the processor and SD/SDIO card both operated at the same voltage level.

Traditionally, the processor and SD/SDIO card both operated at the same voltage level. Figure 1, above, shows the interface between the two devices. The SDIO interface consists of four data signals (DAT0-3), one clock signal (CLK) and one command signal (CMD). The data and command signals are bidirectional, while the clock signal is unidirectional.

The card connector typically has mechanical write-protect and card-detect switches. Their signals are sent back to the processor to implement control functions such as powering up certain sections of the board. To prevent data signals and the command line from floating, pull-up resistors to VDD must be implemented.

Table 1: The system designer must consider trade-offs when choosing a level translator for the SD or MMC interface.

With processors and SDIO peripherals now operating at different interface supply voltages, a level translator has to be added to ensure switching compatibility. Several options are available to achieve proper voltage level translation and, depending on application circumstances, one option may be preferred over another.

For example, system designers have multiple choices of level translation solutions for controlling the bidirectional flow of data and command signals from processor to card. Designers can either use a level translating transceiver with a direction control pin, or use a "directionless" level translator. Both are viable options with various benefits and potential drawbacks.

Figure 2: Fully buffered translator has output transistors that offer several tens of milliamps of DC current with data rate restricted only by the output capacitive load and switching speed of the transistors.

Direction control pin
Figure 2, above, shows a bidirectional translator with a direction control pin or "fully buffered" translator. The output transistors are typically sized to offer several tens of milliamps of DC current, and the data rate is restricted only by the output capacitive load and switching speed of the transistors.

The fully buffered voltage translation solution is shown in an SD/SDIO interface application (Figure 3 below).

Figure 3: One drawback of the fully buffered solution is the multiple processor GPIOs needed for the direction signals that control the data and command lines.

One obvious drawback of this fully buffered solution is the multiple processor GPIOs needed for the direction signals (DAT0-dir, DAT123-dir and CMD-dir) that control the data and command lines. The additional software programming required to properly set the processor signals may also be a disadvantage of implementing this method of level translation.

However, there are several advantages to using a fully buff- ered solution in this application. Card specifications such as MMC 4.1 indicate that a clock can run at a frequency as high as 52MHz with each data bit running at a maximum rate of 52Mbps. SD cards can operate with a clock frequency of up to 50MHz in the high-speed mode.

Figure 4: A 52MHz clock and 52Mbps data signals pass through a fully buffered voltage translator.

These card specs also indicate that edge rate of the clock signal must not take slower than 3ns. Thus, fully buffered solutions must be considered, given that other solutions have restrictions on maximum allowable frequencies and may violate the edge rate requirements on the clock signal.

Figure 4 above shows a 52MHz clock and 52Mbps data signals passing through a fully buffered voltage translator.