Removing deterministic jitter & interference due to noisy power supplies

Sharon Wang and John Abcarius

October 27, 2009

Sharon Wang and John Abcarius

This "Product How-To" article focuses how to use a certain product in an embedded system and is written by a company representative.

Clock generators that employ PLLs are widely used in network equipment for generating high-precision and low-jitter reference clocks, or for maintaining a synchronized network operation.

Most clock oscillators give their jitter or phase noise specification using an ideal, clean power supply. In a practical system environment, the power supply can suffer from interference due to on-board switching supplies or noisy digital ASICs.

To achieve the best performance in a system design, it is important to understand the effects of such interference. First, we examine the basic power supply noise rejection (PSNR) characteristics of a PLL-based clock generator. Following that, we look at how to extract timing jitter information from measurements taken in the frequency domain.

These techniques are then applied, and several different measurement methodologies are compared using lab bench testing. Finally, we summarize the merits of the preferred approach.

PSNR characteristics
A typical PLL clock generator is shown Figure 1 below. Since the output driver can have very different PSNR performance for different types of logic interfaces, the following analysis will focus on the supply noise impact to the PLL itself.

Figure 1: Shown is a typical topology for a PLL clock generator.

Figure 2 below shows the PLL phase model assuming that the power supply noise VN is injected into the PLL/VCO, and the divide ratios, M and N are set to 1.

Figure 2: Shown is the PLL phase model assuming that the power supply noise V N is injected into the PLL/VCO, and the divide ratios, M and N are set to 1

The PLL closed loop transfer function from VN(s) to Φ_o(s) is given by:

For a typical second order PLL:

Here ω_3dB is the PLL 3dB bandwidth, ω_z is the PLL zero frequency, and ω_z << ω_3dB.

The equations above demonstrate that in a PLL clock generator, the power supply noise is rejected by 20dB/dec when the supply interference frequency is greater than the PLL 3dB bandwidth.

For power supply interference frequencies between ω_z and ω_3dB, the output clock phase varies with the power supply interference amplitude as:

As an example, Figure 3 below shows the PSNR characteristics of a PLL for two different settings of the PLL's 3dB bandwidth.

Figure 3: Here are the typical PLL power-supply noise rejection characteristics.

Conversion of power spectrum spurs to DJ
When a single tone sinusoidal signal, f_m, is applied to the power supply of a PLL, it produces a narrow- band phase modulation at the clock output, which can be generally described using Fourier series representation:

Here β is the modulation index representing the maximum phase deviation. For a small index modulation (β<<1), the Bessel function can be approximated as:

Here n = 0 represents the carrier itself. When n = 1, the phase modulated signal is given by:

The equation below demonstrates that, when measuring the double sideband power spectrum S_v(f), if variable x represents the level difference between the carrier at f_o and the fundamental sideband tone at f_m, then:

deviation in radians, the peak-to-peak deterministic jitter caused by this small index phase modulation can be derived as:

This analysis assumes that there is no amplitude modulation contributing to the tone at f_m. In reality, both amplitude and phase modulation can be generated, reducing the accuracy of this approach.

Phase noise spectrum
To avoid the amplitude modulation effect when measuring the power spectrum S_V(f), one can instead calculate the DJ by measuring the spur in the phase noise spectrum while applying a single tone sinusoidal interference on the supply.

With the variable y (dBc) representing the measured single-sideband-phase spurious power at frequency offset f_m, the resultant phase deviation ΔΦ (rad_rms) can be derived as:

It should be noted that the single-sideband phase spectrum in this analysis is not the folded version of the double-sideband spectrum. That is the reason for the 3dB component in the previous equations.

Figure 4: Shown is deterministic jitter vs. phase spurious power.

Figure 4 above shows the relationship between the deterministic jitter and the phase spurious power given by the previous equations.