# Reducing power consumption in CIC filter algorithm designs

A major design goal for cascaded integrator-comb (CIC) filters, especially in conjunction with sample rate conversion, is to minimize their hardware power consumption by reducing data word width and reducing data clock rates wherever possible.

Here we will describe a number of tricks that reduce CIC filter power consumption using nonrecursive structures, by means of polynomial factoring, easing the word width growth problem.

These nonrecursive structures require that the sample rate change R be an integer power of two enhancing computational simplicity through polyphase decomposition, transposed structures, simplified multiplication, and substructure sharing. (*These processes are not complicated; they merely have fancy names.*) In addition we’ll review a nonrecursive scheme that enables sample rate changes other than powers of two.

**Nonrecursive CIC Filters**

The structures of first-order (M = 1) and third-order (M = 3) CIC decimation filters, having a comb delay equal to the sample rate change factor R, are those shown in **Figure 13–66 below**.

**Click on image to enlarge.**

**Figure 13–66 Recursive decimation CIC filters: (a) first-order filter; (b) third-order filter.**The transfer function of an Mth-order decimating CIC filter can be expressed either in a recursive form or a nonrecursive form, as indicated in Eq. (13–119) below.

**Click on image to enlarge.**

Now if the sample rate change factor R is an integer power of two, R = 2_{k} where K is some positive integer, the Eq. (13–119’) Mth-order nonrecursive polynomial form of H_{CIC} can be factored as

**Click on image to enlarge.**

The reward for this factorization is that the CIC filter can then be implemented with K nonrecursive stages as shown in Figure **13–67 below**. This implementation eliminates filter feedback loops with their unpleasant binary word width growth.

**Click on image to enlarge.**

**Figure 13–67 Multistage Mth-order nonrecursive CIC structure.**The data word width does increase in this nonrecursive structure by M bits for each stage, but the sampling rate is reduced by a factor of two for each stage. This nonrecursive structure has been shown to consume less power than the recursive implementation for filter orders greater than three and decimation/interpolation factors larger than eight.

Thus the power savings from sample rate reduction is greater than the power consumption increase due to data word width growth. Happily, further improvements are possible with each stage of this nonrecursive structure. For example, assume we desire an M = fifth-order decimating CIC for Stage 1 in Figure 13–67. In that case, the stage’s transfer function is

**Click on image to enlarge.**

The second step in Eq. (13–121), known as polyphase decomposition, enables a polyphase implementation having two parallel paths as shown in **Figure 13–68 below. **

**Click on image to enlarge.**

**Figure 13–68 Polyphase structure of a single nonrecursive fifth-order CIC stage.**The decimation by two is implemented by routing the odd-index input samples to F

_{A’}(z), and the even-index samples to F

_{B’}(z).

Because we implement decimation by 2 before the filtering, the new polyphase components are F_{A’}(z) = 1 + 10z_{–1} + 5z^{–2}, and F_{B’}(z)= 5 + 10z^{-1} + z^{–2} implemented at half the data rate into the stage. (Reducing data rates as early as possible is a key design goal in the implementation of CIC decimation filters.)

The F_{A’}(z) and F_{B’}(z) polyphase components are implemented in a tapped-delay line fashion and, fortunately, further simplifications are possible.

Let’s consider the F_{A’}(z) polyphase filter component, in a tapped-delay line configuration, shown in **Figure 13–69(a) below**. The transposed version of this filter is presented in Figure 13–69(b) with its flipped coefficient sequence.

**Click on image to enlarge.**

**Figure 13–69 Filter component FA’(z): (a) delay line structure; (b) transposed structure; (c) simplified multiplication; (d) substructure sharing.**The adder in the Figure 13–69(a) must perform two additions per input data sample, while in the transposed structure no adder need perform more than one add per data sample. Thus the transposed structure can operate at a higher speed.

The next improvement uses simplified multiplication, as shown in Figure 13–69(c), by means of arithmetic shifts and adds. Thus a factor of 5 is implemented as 2_{2} + 1, eliminating all multiplications.

Finally, because of the transposed structure, we can use the technique of substructure sharing in Figure 13–69(d) to reduce the hardware component count. Pretty slick! By the way, these nonrecursive filters are still called cascaded integrator-comb filters, even though they have no integrators. Go figure.

**Table 13–7 below** is provided to help the reader avoid computing the polynomial equivalent of several Mth-order nonrecursive stages, as was performed in Eq. (13–121).

**Click on image to enlarge.**

**Table 13–7 Expansions of (1 + z**^{–1})^{M}.

Nonrecursive Prime Factor-R CIC Filters

Nonrecursive Prime Factor-R CIC Filters

The nonrecursive CIC decimation filters described above have the restriction that the R decimation factor must be an integer power of two. That constraint is loosened due to a clever scheme of factoring R into a product of prime numbers.

This multiple prime-factor-R technique is based on the process of factoring integer R into the form **R = 2 ^{p}3^{q}5^{r}7^{s}11^{t} ..**., where

**2, 3, 5, 7, 11**are the prime numbers. (This process is called prime factorization, or prime decomposition, and has been of interest since the days of Euclid.). Then the appropriate number of CIC subfilters are cascaded as shown in

**Figure 13–70(a) below**.

**Click on image to enlarge.**

**Figure 13–70 Multiple prime-factor nonrecursive CIC example: (a) cascaded stage structure; (b) third-order, R = 90, nonrecursive CIC example.**The fortunate condition is that those Mth-order CIC filters are described by

**Click on image to enlarge.**

and so on, enabling nonrecursive implementations. Due to space constraints, the elegant and arduous derivation of this technique is not given here; but this process can illustrated with an example.Assume we desire a third-order CIC filter with a decimation factor of R = 90.

That decimation rate is factored as 90 = (2)(3)(3)(5). So p = 1, q = 2, and r = 1. Our composite CIC filter is implemented as H_{2}(z)H_{3}(z)H_{3} (z)H_{5}(z) shown in Figure 13–70(b).

At first glance the many additions of the Figure 13–70(b) CIC filter appear to aggravate the power consumption of such a filter, but the reduced sample rates significantly reduce power requirements.

If one addition in Section 1 of Figure 13–70(b) consumes P units of power, then Section 1 consumes 3P units of power, and each addition in the first portion of Section 2 consumes P/2 units of power. Each addition in the second portion of Section 2 consumes P/6 of units power, while each addition in Section 3 consumes P/18 units of power.

We have flexibility here because the subfilters in each section of Figure 13–70(b) can be implemented recursively or nonrecursively, as indicated in Eq. (13–122).

In nonrecursive implementations the polyphase decomposition, transposed structures, simplified multiplication, and substructure sharing schemes can be applied. CIC filter design certainly has come a long way since its introduction in the early 1980s.

*Used with the permission of the publisher, Prentice Hall, this on-going series of articles on Embedded.com is based on copyrighted material from "Understanding Digital Signal Processing, Second Edition" by Richard G. Lyons. The book can be purchased on line. *

*Richard Lyons** is a consulting systems engineer and lecturer with Besser Associates. As a lecturer with Besser and an instructor for the University of California Santa Cruz Extension, Lyons has delivered digital signal processing seminars and training course at technical conferences as well at companies such as Motorola, Freescale, Lockheed Martin, Texas Instruments, Conexant, Northrop Grumman, Lucent, Nokia, Qualcomm, Honeywell, National Semiconductor, General Dynamics and Infinion.*

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