Design of a low power high speed differential to single ended converter using feedback

Sanjay Kumar Wadhwa, Freescale Semiconductor

March 4, 2013

Sanjay Kumar Wadhwa, Freescale Semiconductor

Editor’s Note: The author describes the design of a low power, high speed differential to single-ended converter circuit that uses a novel feedback technique to achieve high bandwidth without increasing the current consumption.

The differential to single (D2S) ended converter circuit is an important component in many analog and mixed signal circuits such as Phase Locked Loop (PLL). In a PLL, typically the clock phases generated by voltage controlled oscillator (VCO) do not have rail-to-rail swing.

Typically, a D2S converter is employed to achieve rail-to-rail swing at VCO frequency. For multiphase PLLs, such as those used in clock and data recovery (CDR) circuits and in physical links (PHYs), the power consumed by a D2S converter becomes significant because they are employed with each VCO clock phase.

A conventional cross-coupled D2S converter is shown in Figure 1. INP (positive input) and INN (negative input) are two non-rail-to-rail differential signals. In this circuit, positive feedback ensures rail-to-rail output swing without any leakage current consumption. [1]

However, because of the cross-coupling, there is contention between the pull-up and pull-down transistors because of which it has limited bandwidth and cannot work at high speed (in the range of several MHz). [2]



Figure 2 shows another widely-used high-speed D2S converter. The bandwidth of this circuit is high because of low impendence at PBIAS node (MP1 is diode connected) [3] and absence of any cross-coupling. However, a significant drawback of this circuit is the leakage current flow through MN1 and MP1 when input INP is HIGH. Effectively, when INP is high, there is a resistance of
between VDD (Voltage drain to drain) and GND (ground).



A proposed high-speed D2S converter designed to achieve the same goals is shown in Figure 3. This is a modified version of the circuit shown in Figure 2.



When INP transitions from LOW to HIGH and INN transitions from HIGH to LOW, PBIAS goes low, which turns on MP2 and OUTP goes to VDD. Due to this, MP3 turns off and cuts off the leakage current path through MN1 and MP1.

Initially, since OUTP is low when INP starts transitioning from LOW to HIGH, the proposed high-speed D2S converter is equivalent to the circuit shown in Figure 2 because MP3 is on and PBIAS is close to VDD. To reduce the ON resistance, a large W/L ratio is used for MP3. This helps in quickly charging PBIAS towards VDD when OUTP goes from HIGH to LOW.