How to become a hot commodity (if you're a signal integrity engineer)!

Suresh Subramanian, Cswitch Corp., and Panch Chandrasekaren, Xilinx Inc.

May 24, 2006

Suresh Subramanian, Cswitch Corp., and Panch Chandrasekaren, Xilinx Inc.

High-speed serial links
Today's FPGA devices, such as the Virtex 4FX, provide serial I/O speeds up to 10 Gbps. They come with a wide range of targeted features which can be employed in designing systems with multi-gigabit data rates. Careful signal integrity design is required for proper operation of these systems. Bandwidth limitations in the physical channel, caused by such things as frequency dependent losses, standing waves and mode conversion, can be overcome by selecting the appropriate level and mix of pre-emphasis, voltage swing and receive-side equalization.

Significant degradation of the data can occur after it passes through the transmission path. This degradation includes loss of signal amplitude, reduction of signal rise time and a spreading at the zero crossings. Therefore, it is critical to model the transmission path when designing a high-performance, high-speed serial interconnect system. A typical high-speed serial transmission path will include a Ball-Grid-Array (BGA) package, transmission lines, differential vias, and connectors. It becomes critical to model each piece so that the overall physical channel characteristics can be accurately modeled. An example of a differential pair model on the Xilinx Virtex series FF896 package extracted using 3D field solver based tools is shown in Fig 6. The associated insertion and return loss data of the example in Fig 6 is illustrated by the graph in Fig 7.

A model of a high-bandwidth differential via (GSSG configuration) is shown in Fig 8, while its associated insertion and return loss data is shown in Fig 9. Note that there are many degrees of freedom available to the SI engineer when designing the differential via: via diameter, antipad size, distance to the ground via, size of the ground via, and pad size. Existing EDA tools can be used to optimize these parameters for a desired bandwidth in a given application.

These individual pieces can be combined into a full-channel model. The SI engineer can then perform various what-if analyses to determine the optimal use of features such as pre-emphasis and equalization [4]. This step ensures adequate signal quality at the receiver.

These simulations can be computationally intensive as well as time consuming, especially if circuit simulators like SPICE are involved and thousands of bits must be simulated in order to generate eye diagrams. Both EDA vendors and industry practitioners are working on alternative methodologies, such as using IBIS 4.1/VHDL-AMS models for the drivers, which maintain accuracy while significantly reducing simulation run times. Very good correlation between simulation and measurements has been demonstrated using this approach [5].

Conclusion
The preceding analysis offered a quick and limited survey of the domain of the SI engineer. They enable effective simulation through a nuanced understanding of the effects of each piece of the physical channel, either by itself or in the context of a bus, on overall system performance and reliability. Their expertise, coupled with the money invested in simulation tools and the time invested in simulation, are key to avoiding costly board respins while enjoying the advantages of faster time-to-market.

References

1. Hargin, B. (2004). For Synchronous Signals, Timing is Everything, XCELL Journal, Issue.49, 2004.
2. Schmiit, M, et al., (2004). Simultaneous Switching Noise Analysis for Full-Chip Power Integrity Sign-Off. EPEP 2004 Proceedings.
3. Thierauf, S,C.,(2004). High Speed Circuit Board Signal Integrity. Artech Press.
4. Subramaniam, S., & Murphy, L(2005). 10 Gigabit Channel Virtual Design Kit. DesignCon 2005.
5. Huq, et al., (2005). Multi-Gigabit SerDes System Level Analysis using IBIS v4.1/VHDL-AMS, Mentor User2User Conference, Santa Clara.

Panch Chandrasekaran is marketing manager for Xilinx (www.xilinx.com) high-speed connectivity solutions. Panch's background is in analog and mixed-signal design of 2.5 Gbps and 10 Gbps transceiver chips for telecom applications. He has also held high-speed application engineering positions dealing with multi-gigabit signaling and signal integrity. Panch has a MSEE from University of Central Florida.

Suresh Subramaniam is a Member of Technical Staff at CSwitch Corporation (www.cswitch.com) where he is currently involved in package design and signal integrity simulations. Piror to that he spent more than seven years at Xilinx in various roles ranging from FPGA performance characterization, and signal integrity modeling and design of a number of high speed reference boards (10 Gbps transceivers). He earned his Ph.D in Computational and Cognitive Neurosciences and his MS in Electrical Engineering (VLSI) from the University of Southern California, Los Angeles.