2.5D ICs are more than a stepping stone to 3D ICs

Mike Santarini, Xilinx

March 27, 2012

Mike Santarini, Xilinx

With Xilinx releasing last year the first commercially available 28nm, 2.5D Stacked Silicon Interconnect (SSI) device (the Virtex-7 2000T FPGA) followed by TSMC announcing full manufacturing and assembly support for 2.5D and 3D IC designs, the rest of the IC industry is starting to rev up efforts to make 2.5D and eventually 3D IC technology a mainstream reality.

2.5D has marked advantages of capacity, performance, system space and overall system power consumption over traditional single die implementations—3D promises to have even more. As a refresher, 2.5D, as implemented by Xilinx in the Virtex-7 2000T device, places several die (what Xilinx calls “slices”) side-by-side on a passive silicon interposer.  Meanwhile, the industry envisions 3D ICs will stack two or more die (active-on-active) on top of each other and allow companies to achieve new levels of system integration by stacking the chips normally in a PCB in one or just a few devices (Figure 1).

The vision of a 3D IC is truly promising, but some industry watchers believe the 2.5D market is perhaps being too easily dismissed as a stepping stone to true 3D design. 2.5D has the distinct advantage of being already here today for some companies--and leveraging it takes only minor adjustments to current design flows and seemingly the manufacturing chain.

Herb Reiter, president of consulting firm eda2asic, has been an early champion of stacked silicon as the next paradigm for the semiconductor industry. In last three years, he’s helped with among other things Global Semiconductor Associations efforts in this space and will chair a 2.5/3D focused session at EDPS in Monterey, CA in early April. “It’s been very encouraging to see that many companies are now getting very serious about 2.5D and 3D IC technology,” said Reiter. “When TSMC announced their design flow last year with front to back support for 2.5D IC manufacturing, that helped legitimize the market. I firmly believe there is a train powering up steam and leaving the station. You have to jump on board now or you’ll pay dearly to jump on board later. There are a bunch of companies that are probably kicking themselves even now for not moving on 2.5D and 3D sooner.” 


It certainly isn’t too late, said Reiter. In fact, he has made it his mission to get the EDA, semiconductor and IC assembly and test industries moving together to make 3D IC a reality, as it holds numerous benefits for electronic design for the foreseeable future. “We have to get the whole ecosystem to really understand what is necessary and the challenges they face to make the whole ecosystem complete and to produce high quality products economically,” said Reiter. “I believe many companies can play to their individual strengths and contribute to this new era in design.” But as a veteran of the semiconductor and EDA industries Reiter said that IC design industry very rarely makes radical moves and tends to favor evolutionary changes instead. And one way to get further buy-in from those not already in the 3D IC design chain is to show the value of 2.5D silicon first.

The 2.5D method can allow companies to create devices that far exceed Moore’s Law. It also allows companies to mix and match die on an interposer to essentially create systems on that interposer. For example, Xilinx will soon offer commercially a SSI device that includes a high speed SerDes die alongside programmable logic die. The device will be capable of offering over 400Gbps—far exceeding the requirement of the most advanced communications industry standards, which are calling for the industry transition from 10Gbps to 100Gbps IO data rates.
 
“I firmly believe that 2.5D will be much more compelling and much more widely utilized than 3D for the next several years,” said Reiter. “I believe 3D will overtake 2.5D in revenue especially as it becomes more common in memory chips. 2.5D is already acceptable today and it is easier to implement, easier to cool (especially important when combining logic and DRAM configurations), and, what really matters is that it is quite economical today—true 3D IC design will take quite a few years to go mainstream.”

Ivo Bolsens, Chief Technology Officer at Xilinx, agrees but recalls that pioneering 2.5D wasn’t a cakewalk. Bolsens said that Xilinx’s Labs group started investigating 3D IC technology 8 years ago and that there was a lot of trial and error on every aspect of the technology before Xilinx decided that the 2.5D stacked silicon implementation was the best way to go. “Early on in the process we had actually built a true 3D, active on active, device in the labs. We also built a 2.5D implementation using a passive interposer,” said Bolsens. “Both devices worked, but we had to consider materials, connection types, architectures, designabilty, and manufacturability and cost…there were many considerations before we decided to go with SSI and agree on what we needed to bring the SSI technology to a fully commercially available product.”

Bolsens said he believes active-on-active 3D ICs will one day become a mainstream reality but that a lot of work still needs to be done. Ultimately, said Bolsens, 2.5D is simply better than 3D today on multiple fronts—Design Flow, Device Impact, Cost, Thermal, Testing and Reliability (Table 1). “I’m sure 3D will happen eventually, we plan to use it too, but it will not make 2.5D go away, there are too many advantages in 2.5D.”


Design flow challenges
Bolsens said that Xilinx was able to complete the Virtex-7 2000T device without having to invent any new tools. “I think true 3D will require a revisiting of the entire design flow,” said Bolsens. “You have to think about architectures, partitioning between die layers, co-designing parts on the different dimensions. 2.5D is much more evolutionary. You really have a much more traditional partitioning of your architecture than you do in 3D.” In fact, Bolsens noted that the 2.5D method of placing die side by side on a passive interposer is very much like implementing discrete ICs on a printed circuit board but of course on a much smaller scale. “With 2.5D you have logical boundaries between memory die, logic die, SerDes or whatever die you want to use on the chip,” said Bolsens. “With 3D, you have to look at all the dimensions—there are many variables.”

Device impact
Bolsens believes to move mainstream, 3D ICs will have to overcome formidable device level challenges. “If you’ve seen an electron microscope shot of a 3D IC, you’ll probably be shocked about how big a through silicon via is next to a transistor. It’s like a skyscraper next to tin utility shed. In developing a 3D IC, you have to be very mindful of where you place those TSVs and what impact they will have on the circuitry near them. You can easily create issues with the spreading and uniformity of device characteristics in your die and the rest of the stacked device. You don’t have that issue in 2.5D because the TSVs are in the passive interposer.”

Reiter said that signal and power integrity are both issues in 3D ICs and to a lesser extent in 2.5D. “For example, a high performance processor will have currents in 10s of amps and if you have analog and RF ICs stacked on top, you’ll have to deal with noise, electrical and magnetic interference-- so noise management is an issue that needs to be addressed,” said Reiter. “Similarly if you have TSVs going through the stack and the package pins and have a large number of die, you are drawing significant currents as well. That current draw can of course vary significantly. Most of these die run at about 1V supply voltage. If you have a 2W chip, you are talking about 2 amps but if you have a 50W processor you have 50 amps—it’s like the power of a car battery. This wide requirement in a given stack can mean that power lines can be the source of interference and greatly affect performance and functionality.”

Thermal and reliability
Thermal tolerance is a concern in all advanced IC designs. Bolsens and Reiter said that in a 3D IC, thermal is an especially large concern because different types of die have different tolerances for heat.

In communications and computing applications, it’s not uncommon for devices to dissipate up to 100W. “Today’s 3D stacks would melt away in 100W applications,” said Reiter. “It’s much better if the memory and processors are isolated from each other in a 2.5D configuration. Processors can typically run at 120C junction temperatures, but DRAMs start to encounter problems if you go beyond 85C junction temperatures. DRAMs have an internal mechanism to refresh the memory when it encounters high temperatures. As leakage currents increase exponentially with higher temperatures, DRAMs have to run refresh cycles more frequently. This cycling requires more power and in turn produces more heat. Added to the processor heat, it can become a vicious cycle.”

Bolsens points out that optical devices are also at risk in hot stacks as laser reliability wanes greatly at 80C.

Heating and cooling of die in the stack can also create mechanical stresses, as materials have different thermal coefficients of expansion (TCE). This becomes a greater concern as you place more die in a 3D stack, especially if those die are made of different materials.
 
Reiter said that one way the industry is addressing thermal stress for 3D ICs is by looking at separating each die with a glass interposer. Specifically, Reiter said Georgia Tech is currently working on a method that uses glass as the interposer material, which seemingly offers both electrical insulation as well as thermal shielding. Similarly, IBM and 3M recently announced a partnership to come up with new more thermally conductive materials (Click Here). Both may in future prove to be a good way to take higher-power 3D ICs mainstream.

Bolsens said that Xilinx was able to avoid this issue because the SSI devices have dense and uniform distribution of microbumps to connect die to the interposer (Figure 2). “We have a very uniform spreading of the heat distribution and reliable interconnect,” said Bolsens. “We don’t have to use an exotic underfill that specializes in dissipating heat.”


Testing
Bolsens said that 2.5D hasn’t required any radical changes to testing but 3D ICs will very likely require entirely new test structures as an issue where any defect in a layer of the 3D stack could make the entire device defective. “I think each die in the stack will have to have some form of self test,” said Bolsens. Reiter notes that this will add cost and complexity to each die.

Meanwhile, probing the individual die before assembly also presents challenges for test companies. “FPGA 2.5D structure has great benefits in that by accessing just a few IO paths, we can reach every point in the chip to test it,” said Bolsens. “It’s certainly one of the advantages of having an FPGA die in your 2.5D device.”

Cost
Last but certainly not least, Bolsens said that cost was a big factor in Xilinx choosing 2.5D. “One of the great things we were able to do was leverage existing technologies to make the cost of creating the SSI technology more reasonable,” said Bolsens. “For example, we implemented the interposer in 65nm silicon, which is of course less expensive than 28nm or even 40nm. We also had to put in place the assembly ecosystem but it did come together quite nicely.”

Bolsens and Reiter said that it’s really encouraging that TSMC has taken the bold steps to champion 2.5D and 3D IC design. While TSMC has taken some flack for trying to own the whole manufacturing and assembly flow, which some have categorized as a monopoly play, Bolsens and Reiter point out that TSMC’s investment in 2.5D IC will likely speed up EDA, IP, test, equipment, silicon, and packaging support and perhaps create a short list of requirements and de-facto standards that need to be fulfilled to make 2.5D and eventually 3D IC mainstream.

“What TSMC is doing to pioneer this technology is super,” said Reiter. “This is really exciting technology and it’s just the beginning.”

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